ZHCSRF8 December   2022 TPS3435

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 器件比较
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 详细说明
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Timeout Watchdog Timer
        1. 8.3.1.1 tWD Timer
        2. 8.3.1.2 Watchdog Enable Disable Operation
        3. 8.3.1.3 tSD Watchdog Start Up Delay
        4. 8.3.1.4 SET Pin Behavior
      2. 8.3.2 Manual RESET
      3. 8.3.3 WDO Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Assert Delay
        1. 9.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Timer Functionality
        1. 9.1.2.1 Factory-Programmed Timing Options
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring a Standard Microcontroller for Timeouts
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting the Watchdog Timeout Period
          2. 9.2.1.2.2 Setting Output Assert Delay
          3. 9.2.1.2.3 Setting the Startup Delay
          4. 9.2.1.2.4 Calculating the WDO Pullup Resistor
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

Figure 6-1 Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
Figure 6-3 Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
Figure 6-5 Pin Configuration Option K
DSE Package, 6-Pin WSON,
TPS3435 Top View
Figure 6-2 Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
Figure 6-4 Pin Configuration Option J
DSE Package, 6-Pin WSON,
TPS3435 Top View
Table 6-1 Pin Functions
PIN NAME PIN NUMBER I/O DESCRIPTION
PINOUT A PINOUT B PINOUT C PINOUT J PINOUT K
CRST 3 3 — — 2 I Programmable WDO assert time pin. Connect a capacitor between this pin and GND to program the WDO assert time period. See Section 8.3.3 for more details.
CWD 2 2 — — 1 I Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. See Section 8.3.1.1 for more details.
GND 4 4 4 4 4 — Ground pin
MR 1 — 2 — — I Manual reset pin. A logic low on this pin asserts the WDO output. See Section 8.3.2 for more details.
WDO 7 7 7 5 5 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO is asserted when a watchdog error occurs or MR pin is driven LOW. See Section 8.3.3 for more details.
SET0 5 1 1 1 — I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 8.3.1.4 for more details.
SET1 — 5 5 — — I Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see Section 8.3.1.4 for more details.
VDD 8 8 8 6 6 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.
WD-EN — — 6 2 — I Logic input. Logic high input enables the watchdog monitoring feature. See Section 8.3.1.2 for more details.
WDI 6 6 3 3 3 I Watchdog input. A falling transition (edge) must occur at this pin before the timeout expires in order for WDO to not assert. See Section 8.3.1 for more details.