SLLS907E August   2008  – August 2014 TPD4F003 , TPD6F003 , TPD8F003

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 IEC Clamping Waveforms (clamp voltage measured both at Ch_Out and Ch_In)
      2. 6.6.2 Channel-to-Channel Crosstalk
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Four-, Six-, and Eight-Channel EMI Filtering for Data Ports
      2. 7.3.2 -3 dB Bandwidth of 200 MHz
      3. 7.3.3 Greater Than 25 dB Attenuation at 1 GHz
      4. 7.3.4 Robust ESD Protection Exceeds IEC 61000-4-2
      5. 7.3.5 Pi-Style (C-R-C) Filter Configuration
      6. 7.3.6 Low 10-nA Leakage Current
      7. 7.3.7 Easy Flow-Through Routing
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on All Protected Lines
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DQD|12
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

  • The optimum placement is as close to the connector as possible.
    • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
    • The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
  • Route the protected traces as straight as possible.
  • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
    • Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

This application is typical of an 18-bit RGB display panel layout.

DisplayPanelLayout.gif
Figure 12. TPD6F003 Layout