ZHCSUX9 February   2024 TMUXHS4446

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Timing Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Speed Differential Signal Switching
      2. 6.3.2 Low-Speed SBU Signal Switching
      3. 6.3.3 GPIO and I2C Control Modes
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application: USB-C with DP Alternate Mode - Source
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.4 Device Functional Modes

This section describes how to configure the TMUXHS4446 control pins to configure device modes and mux configurations.

Table 6-1 shows how MODE0 and MODE1 pins are used to set device control configuration modes.

Table 6-1 Control Mode Configuration
Control Mode MODE0 MODE1
GPIO/Pin Control Mode 0 X
I2C (1.8V logic) 1 0
I2C (3.3V logic) 1 1

Table 6-2 shows I2C Register sets. A1 and A0 (Byte 1, bits 2 and 1) are set by pins 35 and 14. CONF[2-0] (Byte 3, bits 2-0) sets the device configurations in I2C mode.

Table 6-2 I2C Control
Byte # & Description Register Bits
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Byte 1, I2C Secondary Target address 1 0 1 0 1 A1 A0 0/1 (W/R)
Byte 2, Device ID (read only) 0 0 0 0 0 0 0 0
Byte 3, Selection control (read/write) 0 0 0 0 0 CONF[2] CONF[1] CONF[0]

Table 6-3 shows how CONF[2:0] pins in GPIO mode and registers Byte 3, bits 2-0 (CONF[2-0]) as shown in Table 6-2 sets mux configurations in source applications.

Table 6-3 High-Speed and Low-Speed Channel Mapping for Source Applications
System-Side Channel Connector-Side Channel Connected To System-Side Channel
Open (powered down) Open (powered on) USB-C USB 3.x DP Alt Mode Receptacle DFP Pin Assignment (Source)
USB SS only USB SS only Flip C, E4 Ln DP C, E Flip4 Ln DP D2 Ln DP + USB SS D Flip2 Ln DP + USB SS
CONF[2:0] = 000 CONF[2:0] = 001 CONF[2:0] = 100 CONF[2:0] = 101 CONF[2:0] = 010 CONF[2:0] = 011 CONF[2:0] = 110 CONF[2:0] = 111
SSTX X X CTX1 CTX2 X X CTX1 CTX2
SSRX X X CRX1 CRX2 X X CRX1 CRX2
DP0 X X X X CRX2 CRX1 CRX2 CRX1
DP1 X X X X CTX2 CTX1 CTX2 CTX1
DP2 X X X X CTX1 CTX2 X X
DP3 X X X X CRX1 CRX2 X X
AUX+ X X X X SBU1 SBU2 SBU1 SBU2
AUX- X X X X SBU2 SBU1 SBU2 SBU1

Figure 6-2 illustrates pictorial view of the TMUXHS4446 mux configurations for a source application based on Table 6-3. In this illustration all signals are differential with both positive and negative pins, but shown as single for brevity.

GUID-20220907-SS0I-SDJQ-HFFP-KP79GPLTLW2C-low.svg Figure 6-2 TMUXHS4446 Signal Flow Diagrams in Different Configurations for Source Applications

The sink side signal flow can also be constructed based on Table 6-4.

Table 6-4 High-Speed and Low-Speed Channel Mapping for Sink Applications
System-Side Channel Connector-Side Channel Connected To System-Side Channel
Open (powered down) Open (powered on) USB-C USB 3.x DP Alt Mode Receptacle UFP Pin Assignment (Sink)
USB SS only USB SS only Flip C4 Ln DP C Flip4 Ln DP D2 Ln DP + USB SS D Flip2 Ln DP + USB SS
CONF[2:0] = 000 CONF[2:0] = 001 CONF[2:0] = 100 CONF[2:0] = 101 CONF[2:0] = 010 CONF[2:0] = 011 CONF[2:0] = 110 CONF[2:0] = 111
SSTX X X CTX1 CTX2 X X CTX1 CTX2
SSRX X X CRX1 CRX2 X X CRX1 CRX2
DP0 X X X X CTX2 CTX1 CTX2 CTX1
DP1 X X X X CRX2 CRX1 CRX2 CRX1
DP2 X X X X CRX1 CRX2 X X
DP3 X X X X CTX1 CTX2 X X
AUX+ X X X X SBU2 SBU1 SBU2 SBU1
AUX- X X X X SBU1 SBU2 SBU1 SBU2