The devices contain four peripheral register spaces. The spaces are categorized as follows:
|
Peripheral Frame 0: |
These are peripherals that are
mapped directly to the CPU memory bus. See Table 8-9. |
|
Peripheral Frame 1: |
These are peripherals that are
mapped to the 32-bit peripheral bus. See Table 8-10. |
|
Peripheral Frame 2: |
These are peripherals that are
mapped to the 16-bit peripheral bus. See Table 8-11. |
|
Peripheral Frame
3: |
These are
peripherals that are mapped to CLA in addition to their respective
Peripheral Frame. See Table 8-12. |
Table 8-9 Peripheral Frame 0
RegistersNAME(1) | ADDRESS RANGE | SIZE (×16) | EALLOW PROTECTED(2) |
---|
Device Emulation Registers | 0x00 0880 to 0x00 0984 | 261 | Yes |
System Power Control Registers | 0x00 0985 to 0x00 0987 | 3 | Yes |
FLASH Registers(3) | 0x00 0A80 to 0x00 0ADF | 96 | Yes |
ADC registers (0 wait read only) | 0x00 0B00 to 0x00 0B0F | 16 | No |
DCSM Zone 1 Registers | 0x00 0B80 to 0x00 0BBF | 64 | Yes |
DCSM Zone 2 Registers | 0x00 0BC0 to 0x00 0BEF | 48 | Yes |
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 Registers | 0x00 0C00 to 0x00 0C3F | 64 | No |
PIE Registers | 0x00 0CE0 to 0x00 0CFF | 32 | No |
PIE Vector Table | 0x00 0D00 to 0x00 0DFF | 256 | No |
CLA Registers | 0x00 1400 to 0x00 147F | 128 | Yes |
CLA to CPU Message RAM (CPU writes ignored) | 0x00 1480 to 0x00 14FF | 128 | NA |
CPU to CLA Message RAM (CLA writes ignored) | 0x00 1500 to 0x00 157F | 128 | NA |
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Dual Code Security Module.
Table 8-10 Peripheral Frame 1 RegistersNAME | ADDRESS RANGE | SIZE (×16) | EALLOW PROTECTED |
---|
eCAN-A Registers | 0x00 6000 to 0x00 61FF | 512 | (1) |
eCAP1 Registers | 0x00 6A00 to 0x00 6A1F | 32 | No |
eQEP1 Registers | 0x00 6B00 to 0x00 6B3F | 64 | (1) |
GPIO Registers | 0x00 6F80 to 0x00 6FFF | 128 | (1) |
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 8-11 Peripheral Frame 2
Registers
NAME |
ADDRESS RANGE |
SIZE (×16) |
EALLOW
PROTECTED |
System Control Registers |
0x00 7010 to 0x00 702F |
32 |
Yes |
SPI-A Registers |
0x00 7040 to 0x00 704F |
16 |
No |
SCI-A Registers |
0x00 7050 to 0x00 705F |
16 |
No |
SCI-B Registers |
0x00 7750 to 0x00 775F |
16 |
No |
SCI-C Registers |
0x00 7770 to 0x00 777F |
16 |
No |
NMI Watchdog Interrupt
Registers |
0x00 7060 to 0x00 706F |
16 |
Yes |
External Interrupt Registers |
0x00 7070 to 0x00 707F |
16 |
Yes |
ADC Registers |
0x00 7100 to 0x00 717F |
128 |
(1) |
I2C-A Registers |
0x00 7900 to 0x00 793F |
64 |
(1) |
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 8-12 Peripheral Frame 3 RegistersNAME | ADDRESS RANGE | SIZE (×16) | EALLOW PROTECTED |
---|
ADC registers (0 wait read only) | 0x00 0B00 to 0x00 0B0F | 16 | No |
DAC Control Registers | 0x00 6400 to 0x00 640F | 16 | Yes |
DAC, PGA, Comparator, and Filter Enable Registers | 0x00 6410 to 0x00 641F | 16 | Yes |
SWITCH Registers | 0x00 6420 to 0x00 642F | 16 | Yes |
Digital Filter and Comparator Control Registers | 0x00 6430 to 0x00 647F | 80 | Yes |
LOCK Registers | 0x00 64F0 to 0x00 64FF | 16 | Yes |
ePWM1 registers | 0x00 6800 to 0x00 683F | 64 | (1) |
ePWM2 registers | 0x00 6840 to 0x00 687F | 64 | (1) |
ePWM3 registers | 0x00 6880 to 0x00 68BF | 64 | (1) |
ePWM4 registers | 0x00 68C0 to 0x00 68FF | 64 | (1) |
ePWM5 registers | 0x00 6900 to 0x00 693F | 64 | (1) |
ePWM6 registers | 0x00 6940 to 0x00 697F | 64 | (1) |
ePWM7 registers | 0x00 6980 to 0x00 69BF | 64 | (1) |
eCAP1 Registers | 0x00 6A00 to 0x00 6A1F | 32 | No |
eQEP1 Registers | 0x00 6B00 to 0x00 6B3F | 64 | (1) |
(1) Some registers are EALLOW protected. See the module reference guide for more information.