ZHCSAH6F November   2012  – September 2021 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052F , TMS320F28052M , TMS320F28053 , TMS320F28054 , TMS320F28054F , TMS320F28054M , TMS320F28055

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 功能方框图
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for PN Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements - PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements - PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 60-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator
      3. 8.1.3  Memory Bus (Harvard Bus Architecture)
      4. 8.1.4  Peripheral Bus
      5. 8.1.5  Real-Time JTAG and Analysis
      6. 8.1.6  Flash
      7. 8.1.7  M0, M1 SARAMs
      8. 8.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 8.1.9  Boot ROM
        1. 8.1.9.1 Emulation Boot
        2. 8.1.9.2 GetMode
        3. 8.1.9.3 Peripheral Pins Used by the Bootloader
      10. 8.1.10 Security
      11. 8.1.11 Peripheral Interrupt Expansion Block
      12. 8.1.12 External Interrupts (XINT1 to XINT3)
      13. 8.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 8.1.14 Watchdog
      15. 8.1.15 Peripheral Clocking
      16. 8.1.16 Low-power Modes
      17. 8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 8.1.18 General-Purpose Input/Output Multiplexer
      19. 8.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 8.1.20 Control Peripherals
      21. 8.1.21 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Map
    4. 8.4 Device Emulation Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero-Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 8.6.5 CPU-watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  Control Law Accelerator
        1. 8.9.1.1 CLA Device-Specific Information
        2. 8.9.1.2 CLA Register Descriptions
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter
          1. 8.9.2.1.1 ADC Device-Specific Information
          2. 8.9.2.1.2 ADC Electrical Data/Timing
            1. 8.9.2.1.2.1 ADC Electrical Characteristics
            2. 8.9.2.1.2.2 ADC Power Modes
            3. 8.9.2.1.2.3 External ADC Start-of-Conversion Electrical Data/Timing
              1. 8.9.2.1.2.3.1 External ADC Start-of-Conversion Switching Characteristics
            4. 8.9.2.1.2.4 Internal Temperature Sensor
              1. 8.9.2.1.2.4.1 Temperature Sensor Coefficient
            5. 8.9.2.1.2.5 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.2.5.1 ADC Power-Up Delays
            6. 8.9.2.1.2.6 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 Analog Front End
          1. 8.9.2.2.1 AFE Device-Specific Information
          2. 8.9.2.2.2 AFE Register Descriptions
          3. 8.9.2.2.3 PGA Electrical Data/Timing
          4. 8.9.2.2.4 Comparator Block Electrical Data/Timing
            1. 8.9.2.2.4.1 Electrical Characteristics of the Comparator/DAC
          5. 8.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. 8.9.2.2.5.1 Electrical Characteristics of VREFOUT Buffered DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface
        1. 8.9.4.1 SPI Device-Specific Information
        2. 8.9.4.2 SPI Register Descriptions
        3. 8.9.4.3 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.3.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.3.2 SPI Master Mode External Timing (Clock Phase = 1)
        4. 8.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.4.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.4.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface
        1. 8.9.5.1 SCI Device-Specific Information
        2. 8.9.5.2 SCI Register Descriptions
      6. 8.9.6  Enhanced Controller Area Network
        1. 8.9.6.1 eCAN Device-Specific Information
        2. 8.9.6.2 eCAN Register Descriptions
      7. 8.9.7  Inter-Integrated Circuit
        1. 8.9.7.1 I2C Device-Specific Information
        2. 8.9.7.2 I2C Register Descriptions
        3. 8.9.7.3 I2C Electrical Data/Timing
          1. 8.9.7.3.1 I2C Timing Requirements
          2. 8.9.7.3.2 I2C Switching Characteristics
      8. 8.9.8  Enhanced Pulse Width Modulator
        1. 8.9.8.1 ePWM Device-Specific Information
        2. 8.9.8.2 ePWM Register Descriptions
        3. 8.9.8.3 ePWM Electrical Data/Timing
          1. 8.9.8.3.1 ePWM Timing Requirements
          2. 8.9.8.3.2 ePWM Switching Characteristics
          3. 8.9.8.3.3 Trip-Zone Input Timing
            1. 8.9.8.3.3.1 Trip-Zone Input Timing Requirements
      9. 8.9.9  Enhanced Capture Module
        1. 8.9.9.1 eCAP Module Device-Specific Information
        2. 8.9.9.2 eCAP Module Register Descriptions
        3. 8.9.9.3 eCAP Module Electrical Data/Timing
          1. 8.9.9.3.1 eCAP Timing Requirement
          2. 8.9.9.3.2 eCAP Switching Characteristics
      10. 8.9.10 Enhanced Quadrature Encoder Pulse
        1. 8.9.10.1 eQEP Device-Specific Information
        2. 8.9.10.2 eQEP Register Descriptions
        3. 8.9.10.3 eQEP Electrical Data/Timing
          1. 8.9.10.3.1 eQEP Timing Requirements
          2. 8.9.10.3.2 eQEP Switching Characteristics
      11. 8.9.11 JTAG Port
        1. 8.9.11.1 JTAG Port Device-Specific Information
      12. 8.9.12 General-Purpose Input/Output
        1. 8.9.12.1 GPIO Device-Specific Information
        2. 8.9.12.2 GPIO Register Descriptions
        3. 8.9.12.3 GPIO Electrical Data/Timing
          1. 8.9.12.3.1 GPIO - Output Timing
            1. 8.9.12.3.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.12.3.2 GPIO - Input Timing
            1. 8.9.12.3.2.1 General-Purpose Input Timing Requirements
          3. 8.9.12.3.3 Sampling Window Width for Input Signals
          4. 8.9.12.3.4 Low-Power Mode Wakeup Timing
            1. 8.9.12.3.4.1 IDLE Mode Timing Requirements
            2. 8.9.12.3.4.2 IDLE Mode Switching Characteristics
            3. 8.9.12.3.4.3 STANDBY Mode Timing Requirements
            4. 8.9.12.3.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.12.3.4.5 HALT Mode Timing Requirements
            6. 8.9.12.3.4.6 HALT Mode Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

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8.9.8.2 ePWM Register Descriptions

Table 8-45 and Table 8-46 show the complete ePWM register set per module.

Table 8-45 ePWM1–ePWM4 Control and Status Registers
NAMEePWM1ePWM2ePWM3ePWM4SIZE (×16) / #SHADOWDESCRIPTION
TBCTL0x68000x68400x68800x68C01 / 0Time Base Control register
TBSTS0x68010x68410x68810x68C11 / 0Time Base Status register
Reserved0x68020x68420x68820x68C21 / 0Reserved
TBPHS0x68030x68430x68830x68C31 / 0Time Base Phase register
TBCTR0x68040x68440x68840x68C41 / 0Time Base Counter register
TBPRD0x68050x68450x68850x68C51 / 1Time Base Period Register Set
Reserved0x68060x68460x68860x68C61 / 1Reserved
CMPCTL0x68070x68470x68870x68C71 / 0Counter Compare Control register
Reserved0x68080x68480x68880x68C81 / 1Reserved
CMPA0x68090x68490x68890x68C91 / 1Counter Compare A Register Set
CMPB0x680A0x684A0x688A0x68CA1 / 1Counter Compare B Register Set
AQCTLA0x680B0x684B0x688B0x68CB1 / 0Action Qualifier Control register for output A
AQCTLB0x680C0x684C0x688C0x68CC1 / 0Action Qualifier Control register for output B
AQSFRC0x680D0x684D0x688D0x68CD1 / 0Action Qualifier Software Force register
AQCSFRC0x680E0x684E0x688E0x68CE1 / 1Action Qualifier Continuous S/W Force Register Set
DBCTL0x680F0x684F0x688F0x68CF1 / 1Dead-Band Generator Control register
DBRED0x68100x68500x68900x68D01 / 0Dead-Band Generator Rising Edge Delay Count register
DBFED0x68110x68510x68910x68D11 / 0Dead-Band Generator Falling Edge Delay Count register
TZSEL0x68120x68520x68920x68D21 / 0Trip Zone Select register(1)
TZDCSEL0x68130x68530x68930x98D31 / 0Trip Zone Digital Compare register
TZCTL0x68140x68540x68940x68D41 / 0Trip Zone Control register(1)
TZEINT0x68150x68550x68950x68D51 / 0Trip Zone Enable Interrupt register(1)
TZFLG0x68160x68560x68960x68D61 / 0Trip Zone Flag register (1)
TZCLR0x68170x68570x68970x68D71 / 0Trip Zone Clear register(1)
TZFRC0x68180x68580x68980x68D81 / 0Trip Zone Force register(1)
ETSEL0x68190x68590x68990x68D91 / 0Event Trigger Selection register
ETPS0x681A0x685A0x689A0x68DA1 / 0Event Trigger Prescale register
ETFLG0x681B0x685B0x689B0x68DB1 / 0Event Trigger Flag register
ETCLR0x681C0x685C0x689C0x68DC1 / 0Event Trigger Clear register
ETFRC0x681D0x685D0x689D0x68DD1 / 0Event Trigger Force register
PCCTL0x681E0x685E0x689E0x68DE1 / 0PWM Chopper Control register
Reserved0x68200x68600x68A00x68E01 / 0Reserved
Reserved0x6821---1 / 0Reserved
Reserved0x6826---1 / 0Reserved
Reserved0x68280x68680x68A80x68E81 / 0Reserved
Reserved0x682A0x686A0x68AA0x68EA1 / W(2)Reserved
TBPRDM0x682B0x686B0x68AB0x68EB1 / W(2)Time Base Period Register Mirror
Reserved0x682C0x686C0x68AC0x68EC1 / W(2)Reserved
CMPAM0x682D0x686D0x68AD0x68ED1 / W(2)Compare A Register Mirror
DCTRIPSEL0x68300x68700x68B00x68F01 / 0Digital Compare Trip Select register (1)
DCACTL0x68310x68710x68B10x68F11 / 0Digital Compare A Control register(1)
DCBCTL0x68320x68720x68B20x68F21 / 0Digital Compare B Control register(1)
DCFCTL0x68330x68730x68B30x68F31 / 0Digital Compare Filter Control register(1)
DCCAPCT0x68340x68740x68B40x68F41 / 0Digital Compare Capture Control register(1)
DCFOFFSET0x68350x68750x68B50x68F51 / 1Digital Compare Filter Offset register
DCFOFFSETCNT0x68360x68760x68B60x68F61 / 0Digital Compare Filter Offset Counter register
DCFWINDOW0x68370x68770x68B70x68F71 / 0Digital Compare Filter Window register
DCFWINDOWCNT0x68380x68780x68B80x68F81 / 0Digital Compare Filter Window Counter register
DCCAP0x68390x68790x68B90x68F91 / 1Digital Compare Counter Capture register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
Table 8-46 ePWM5–ePWM7 Control and Status Registers
NAMEePWM5ePWM6ePWM7SIZE (×16) / #SHADOWDESCRIPTION
TBCTL0x69000x69400x69801 / 0Time Base Control register
TBSTS0x69010x69410x69811 / 0Time Base Status register
Reserved0x69020x69420x69821 / 0Reserved
TBPHS0x69030x69430x69831 / 0Time Base Phase register
TBCTR0x69040x69440x69841 / 0Time Base Counter register
TBPRD0x69050x69450x69851 / 1Time Base Period Register Set
Reserved0x69060x69460x69861 / 1Reserved
CMPCTL0x69070x69470x69871 / 0Counter Compare Control register
Reserved0x69080x69480x69881 / 1Reserved
CMPA0x69090x69490x69891 / 1Counter Compare A Register Set
CMPB0x690A0x694A0x698A1 / 1Counter Compare B Register Set
AQCTLA0x690B0x694B0x698B1 / 0Action Qualifier Control register for output A
AQCTLB0x690C0x694C0x698C1 / 0Action Qualifier Control register for output B
AQSFRC0x690D0x694D0x698D1 / 0Action Qualifier Software Force register
AQCSFRC0x690E0x694E0x698E1 / 1Action Qualifier Continuous S/W Force Register Set
DBCTL0x690F0x694F0x698F1 / 1Dead-Band Generator Control register
DBRED0x69100x69500x69901 / 0Dead-Band Generator Rising Edge Delay Count register
DBFED0x69110x69510x69911 / 0Dead-Band Generator Falling Edge Delay Count register
TZSEL0x69120x69520x69921 / 0Trip Zone Select register(1)
TZDCSEL0x69130x69530x69931 / 0Trip Zone Digital Compare register
TZCTL0x69140x69540x69941 / 0Trip Zone Control register(1)
TZEINT0x69150x69550x69951 / 0Trip Zone Enable Interrupt register(1)
TZFLG0x69160x69560x69961 / 0Trip Zone Flag register (1)
TZCLR0x69170x69570x69971 / 0Trip Zone Clear register(1)
TZFRC0x69180x69580x69981 / 0Trip Zone Force register(1)
ETSEL0x69190x69590x69991 / 0Event Trigger Selection register
ETPS0x691A0x695A0x699A1 / 0Event Trigger Prescale register
ETFLG0x691B0x695B0x699B1 / 0Event Trigger Flag register
ETCLR0x691C0x695C0x699C1 / 0Event Trigger Clear register
ETFRC0x691D0x695D0x699D1 / 0Event Trigger Force register
PCCTL0x691E0x695E0x699E1 / 0PWM Chopper Control register
Reserved0x69200x69600x69A01 / 0Reserved
Reserved---1 / 0Reserved
Reserved---1 / 0Reserved
Reserved0x69280x69680x69A81 / 0Reserved
Reserved0x692A0x696A0x69AA1 / W(2)Reserved
TBPRDM0x692B0x696B0x69AB1 / W(2)Time Base Period Register Mirror
Reserved0x692C0x696C0x69AC1 / W(2)Reserved
CMPAM0x692D0x696D0x69AD1 / W(2)Compare A Register Mirror
DCTRIPSEL0x69300x69700x69B01 / 0Digital Compare Trip Select register (1)
DCACTL0x69310x69710x69B11 / 0Digital Compare A Control register(1)
DCBCTL0x69320x69720x69B21 / 0Digital Compare B Control register(1)
DCFCTL0x69330x69730x69B31 / 0Digital Compare Filter Control register(1)
DCCAPCT0x69340x69740x69B41 / 0Digital Compare Capture Control register(1)
DCFOFFSET0x69350x69750x69B51 / 1Digital Compare Filter Offset register
DCFOFFSETCNT0x69360x69760x69B61 / 0Digital Compare Filter Offset Counter register
DCFWINDOW0x69370x69770x69B71 / 0Digital Compare Filter Window register
DCFWINDOWCNT0x69380x69780x69B81 / 0Digital Compare Filter Window Counter register
DCCAP0x69390x69790x69B91 / 1Digital Compare Counter Capture register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register