SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

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9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM

These application curves are taken with the TLV840EVM and they display a change in reset delay time with different capacitor values. The output reset delay time was designed with the ease of programability for the customer. Figure 9-3 displays an output reset delay time of 57.6 μs with no capacitor on the CT pin. Figure 9-4 and Figure 9-5 have output reset delay times of 5.42 ms and 56.8 ms, respectively. Both the output delay times and capacitors used resulted in an order of magnitude difference. Please see the TLV840EVM User Guide for more information.

GUID-E0AAC521-59F0-4368-B0A9-F82C413025DA-low.gifFigure 9-3 TLV840EVM RESET Time Delay (tD) with No Capacitor
GUID-D6F7AF71-4D5D-4CA1-9138-260C9BC512BC-low.gifFigure 9-5 TLV840EVM RESET Time Delay (tD) with 0.1-µF Capacitor
GUID-20201208-CA0I-KMRM-PRPG-WP9ZSG8J76JQ-low.svgFigure 9-4 TLV840EVM RESET Time Delay (tD) with 0.01-µF Capacitor