ZHCSKC8 October   2019 TLV6003

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      PIR 运动检测器缓冲器
      2.      失调电压与温度间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information – TLV6003
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reverse-Battery Protection
      2. 7.3.2 Common-Mode Input Range
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Drive a Capacitive Load
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Common-Mode Input Range

The TLV6003 has rail-to-rail inputs and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V, a PNP differential pair provides the gain.

For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair provide the gain.

This special combination of a NPN and PNP differential pair enables the inputs to be taken 5 V greater than VCC. As the inputs rise to greater than VCC, the NPNs change from functioning as transistors to functioning as diodes. This change leads to an increase in input bias current. The second PNP differential pair continues to function normally as the inputs exceed VCC.

The TLV6003 has a negative common-mode input voltage range that can fall to less than VGND by 100 mV. If the inputs are taken to less than VGND – 0.1, reduced open-loop gain will be observed.