ZHCSLN7E august   2020  – july 2023 TLV3604 , TLV3605 , TLV3607

PRODMIX  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Configurations: TLV3604 and TLV3605
    2. 5.1 Pin Configuration: TLV3607
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VCCI = VCCO = 2.5 V to 5 V)
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Rail-to-Rail Inputs
      2. 7.4.2 LVDS Output
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Comparator Inputs
      2. 8.1.2 Capacitive Loads
      3. 8.1.3 Latch Functionality
      4. 8.1.4 Adjustable Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Non-Inverting Comparator With Hysteresis
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Optical Receiver
      3. 8.2.3 Logic Clock Source to LVDS Transceiver
      4. 8.2.4 External Trigger Function for Oscilloscopes
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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5.1 Pin Configuration: TLV3607

GUID-20230113-SS0I-7G4L-L2Q9-KTNLN3GNN14Q-low.svgFigure 5-3 RTE Package
16-Pin WQFN with Exposed Thermal Pad
Top View
Table 5-2 Pin Functions: TLV3607
PINI/ODESCRIPTION
NAMETLV3607
IN+A1IChannel A non-inverting input
IN–A2IChannel A inverting input
IN–B3IChannel B inverting input
IN+B4IChannel B non-inverting input
OUT+A12OChannel A non-inverting output
OUT–A11OChannel A inverting output
OUT–B10OChannel B inverting output
OUT+B9OChannel B non-inverting output
VEE6, 14INegative power supply
VCCI5IPositive input section power supply
VCCO13IPositive output section power supply
SHDNA16IChannel A shutdown control (active low)
SHDNB8IChannel B shutdown control (active low)
LE/HYSA15IChannel A latch enable (active low) and adjustable hysteresis control
LE/HYSB7IChannel B latch enable (active low) and adjustable hysteresis control