ZHCSDU7C 数据表 | 德州仪器 TI.com.cn

ZHCSDU7C July 2015 – September 2017 TLK10031

PRODUCTION DATA.

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CTR|144
- MPBGA06A

散热焊盘机械数据 (封装 | 引脚)

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		VALUE		UNIT
		MIN	MAX	UNIT
Supply voltage	DVDD, VDD_LS/HS, VDDT_LS/HS, VPP, VDDD	–0.3	1.4	V
Supply voltage	VDDR_LS/HS, VDDO[1:0]	–0.3	2.2	V
Input Voltage, V_I	LVCMOS, CML, Analog	–0.3	Supply + 0.3	V
Operating Junction Temperature			105	°C
Characterized free-air operating temperature range		–40	85	°C
Storage temperature, T_stg		-65	150	°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground (VSS).

5.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾		±1000	V
V_(ESD)	Electrostatic discharge	Charged Device Model (CDM), per JESD22-C101⁽²⁾		±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

PARAMETER			TEST CONDITIONS	MIN	NOM	MAX	UNIT
	Digital / analog supply voltages	VDDD, VDD_LS/HS, DVDD, VDDT_LS/HS, VPP		0.95	1.00	1.05	V
	SERDES PLL regulator voltage	VDDR_LS/HS	1.5V Nominal	1.425	1.5	1.575	V
	SERDES PLL regulator voltage	VDDR_LS/HS	1.8V Nominal	1.71	1.8	1.89	V
	LVCMOS I/O supply voltage	VDDO[1:0]	1.5V Nominal	1.425	1.5	1.575	V
	LVCMOS I/O supply voltage	VDDO[1:0]	1.8V Nominal	1.71	1.8	1.89	V
I_DD	Supply current	VDDD	10.3 Gbps			650	mA
		VDDA_LS/HS				650
		DVDD + VPP				700
		VDDT_LS/HS				600
		VDDRA_LS				70
		VDDRA_HS				70
		VDDO[1:0]				10
P_D	Power dissipation		Nominal		800		mW
P_D	Power dissipation		Worst case supply voltage, temperature, and process. 10GBASE-KR, channel active, default swing and Clkout settings			1.15	W
I_SD	Shutdown current	VDDD	PDTRXA_N Asserted			300	mA
		VDDA				85
		DVDD + VPP				250
		VDDT				65
		VDDRA_HS/LS				7
		VDDO				5
J_R	REFCLK0P/N, REFCLK1P/N Random Jitter		12kHz to 20MHz			1	ps

5.4 Thermal Information

NAME	DESCRIPTION	VALUE	UNIT
R_θJA	Junction-to-free air	25.5	°C/W
ω_JT	Junction-to-package top	1.8
ω_JB	Junction-to-board	13.7
Custom Typical Application Board⁽¹⁾
R_θJA	Junction-to-free air	24.5	°C/W
ω_JT	Junction-to-package top	0.9
ω_JB	Junction-to-board	11

(1) Custom Typical Application Board Characteristics:

10x15 inches
12 layer
- 8 power/ground layers – 95% copper (1oz)
- 4 signal layers – 20% copper (1oz)

Ψ_JB= (T_J – T_B)/(Total Device Power Dissipation)
T_J = Device Junction Temperature
T_B = Temperature of PCB 1 mm from device edge.

Ψ_JT= (T_J – T_C)/(Total Device Power Dissipation)
T_J = Device Junction Temperature
T_C = Hottest temperature on the case of the package.

5.5 Electrical Characteristics: High Speed Side Serial Transmitter

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
V_OD(p-p)	TX Output differential peak-to-peak voltage swing, transmitter enabled	SWING = 0000	50	130	220	mV_pp
		SWING = 0001	110	220	320
		SWING = 0010	180	300	430
		SWING = 0011	250	390	540
		SWING = 0100	320	480	650
		SWING = 0101	390	570	770
		SWING = 0110	460	660	880
		SWING = 0111	530	750	1000
		SWING = 1000	590	830	1100
		SWING = 1001	660	930	1220
		SWING = 1010	740	1020	1320
		SWING = 1011	820	1110	1430
		SWING = 1100	890	1180	1520
		SWING = 1101	970	1270	1610
		SWING = 1110	1060	1340	1680
		SWING = 1111	1090	1400	1740
		Transmitter disabled			30
V_pre/post	TX Output pre/post cursor emphasis voltage	See register bits TWPOST1, TWPOST2, and TWPRE for de-emphasis settings. See Figure 6-2	–17.5/ –37.5%		+17.5/ +37.5%
V_CMT	TX Output common mode voltage	100-Ω differential termination. DC-coupled.		V_DDT - 0.25 * V_OD(p-p)		mV
t_skew	Intra-pair output skew	Serial Rate = 9.8304 Gbps			0.045	UI
T_r, T_f	Differential output signal rise, fall time (20% to 80%), Differential Load = 100Ω		24			ps
J_T1	Serial output total jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates)	Serial Rate ≤ 3.072Gbps			0.35	UI_pp
J_T1		Serial Rate > 3.072Gbps			0.28	UI_pp
J_D1	Serial output deterministic jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates)	Serial Rate ≤ 3.072Gbps			0.17	UI_pp
J_D1		Serial Rate > 3.072Gbps			0.15	UI_pp
J_R1	Serial output random jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates)	Serial Rate > 3.072Gbps			0.15	UI_pp
J_T2	Serial output total jitter (CPRI E.12.HV)	Serial Rate = 1.2288Gbps			0.279	UI_pp
J_D2	Serial output deterministic jitter (CPRI E.12.HV)	Serial Rate = 1.2288Gbps			0.14	UI_pp
SDD22	Differential output return loss	50 MHz < f < 2.5 GHz			9	dB
SDD22	Differential output return loss	2.5 GHz < f < 7.5 GHz			See ⁽¹⁾	dB
SCC22	Common-mode output return loss	50 MHz < f < 2.5 GHz			6	dB
SCC22	Common-mode output return loss	2.5 GHz < f < 7.5 GHz			See ⁽²⁾	dB
T_(LATENCY)	Transmit path latency	10GBASE-KR mode	see Figure 7-6
		1GBASE-KX mode	see Figure 7-9
		General Purpose mode	see Figure 7-13

(1) Differential input return loss, SDD22 = 9 – 12 log₁₀(f / 2500MHz)) dB

(2) Common-mode output return loss, SDD22 = 6 – 12 log10(f / 2500MHz)) dB

5.6 Electrical Characteristics: High Speed Side Serial Receiver

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_ID	RX Input differential voltage, \|RXP – RXN\|	Full Rate, AC Coupled	50	600	mV
V_ID	RX Input differential voltage, \|RXP – RXN\|	Half/Quarter/Eighth Rate, AC Coupled	50	800	mV
V_ID(pp)	RX Input differential peak-to-peak voltage swing, 2×\|RXP – RXN\|	Full Rate, AC Coupled	100	1200	mV_pp
V_ID(pp)		Half/Quarter/Eighth Rate, AC Coupled	100	1600	mV_pp
C_I	RX Input capacitance			2	pF
J_TOL	10GBASE-KR Jitter tolerance, test channel with mTC =1 (see Figure 5-1 for attenuation curve), PRBS31 test pattern at 10.3125 Gbps	Applied sinusoidal jitter		0.115	UI_pp
		Applied random jitter		0.130
		Applied duty cycle distortion		0.035
		Broadband noise amplitude (RMS)		5.2
SDD11	Differential input return loss	50 MHz < f < 2.5 GHz	9		dB
SDD11	Differential input return loss	2.5 GHz < f < 7.5 GHz	See ⁽¹⁾		dB
t_skew	Intra-pair input skew			0.23	UI
t_(LATENCY)	Receive path latency	10GBASE-KR mode	see Figure 7-6
		1GBASE-KX mode	see Figure 7-9
		General Purpose mode	see Figure 7-13

(1) Differential input return loss, SDD11 = 9 – 12 log₁₀(f / 2.5GHz)) dB

5.7 Electrical Characteristics: Low Speed Side Serial Transmitter

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
V_OD(pp)	Transmitter output differential peak-to-peak voltage swing	SWING = 000	110	190	280	mVpp
		SWING = 001	280	380	490
		SWING = 010	420	560	700
		SWING = 011	560	710	870
		SWING = 100	690	850	1020
		SWING = 101	760	950	1150
		SWING = 110	800	1010	1230
		SWING = 111	830	1050	1270
DE	Transmitter output de-emphasis voltage swing reduction	DE = 0000		0		dB
		DE = 0001		0.42
		DE = 0010		0.87
		DE = 0011		1.34
		DE = 0100		1.83
		DE = 0101		2.36
		DE = 0110		2.92
		DE = 0111		3.52
		DE = 1000		4.16
		DE = 1001		4.86
		DE = 1010		5.61
		DE = 1011		6.44
		DE = 1100		7.35
		DE = 1101		8.38
		DE = 1110		9.54
		DE = 1111		10.87
V_CMT	Transmitter output common mode voltage	100-Ω differential termination. DC-coupled.		V_DDT - 0.5 * V_OD(p-p)		mV
t_skew	Intra-pair output skew				0.045	UI
t_R, t_F	Differential output signal rise, fall time (20% to 80%) Differential Load = 100Ω		30			ps
J_T	Serial output total jitter				0.35	UI
J_D	Serial output deterministic jitter				0.17	UI
t_skew	Lane-to-lane output skew				50	ps

5.8 Electrical Characteristics: Low Speed Side Serial Receiver

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_ID	Receiver input differential voltage, \|INP – INN\|	Full Rate, AC Coupled	50	600	mV
V_ID	Receiver input differential voltage, \|INP – INN\|	Half/Quarter Rate, AC Coupled	50	800	mV
V_ID(pp)	Receiver input differential peak-to-peak voltage swing 2×\|INP – INN\|	Full Rate, AC Coupled	100	1200	mV_dfpp
V_ID(pp)		Half/Quarter Rate, AC Coupled	100	1600	mV_dfpp
C_I	Receiver input capacitance			2	pF
J_TOL	Jitter tolerance, total jitter at serial input (DJ + RJ) (BER 10^-15)	Zero crossing, Half/Quarter Rate		0.66	UI_p-p
J_TOL		Zero crossing, Full Rate		0.65	UI_p-p
J_DR	Serial input deterministic jitter (BER 10^-15)	Zero crossing, Half/Quarter Rate		0.50	UI_p-p
J_DR	Serial input deterministic jitter (BER 10^-15)	Zero crossing, Full Rate		0.35	UI_p-p
t_skew	Intra-pair input skew			0.23	UI
t_lane-skew	Lane-to-lane input skew			30	UI

5.9 Electrical Characteristics: LVCMOS (VDDO):

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_OH	High-level output voltage	I_OH = 2 mA, Driver Enabled (1.8V)	VDDO – 0.45	VDDO	V
V_OH	High-level output voltage	I_OH = 2 mA, Driver Enabled (1.5V)	0.75 × VDDO	VDDO	V
V_OL	Low-level output voltage	I_OL = –2 mA, Driver Enabled (1.8V)	0	0.45	V
V_OL	Low-level output voltage	I_OL = –2 mA, Driver Enabled (1.5V)	0	0.25 × VDDO	V
V_IH	High-level input voltage		0.65 × VDDO	VDDO + 0.3	V
V_IL	Low-level input voltage		–0.3	0.35 × VDDO	V
I_IH, I_IL	Receiver only	Low/High Input Current		±170	µA
I_OZ	Driver only	Driver Disabled		±25	µA
I_OZ	Driver/Receiver With Pullup/Pulldown	Driver disabled With Pull Up/Down Enabled		±195	µA
C_IN	Input capacitance			3	pF

5.10 Electrical Characteristics: Clocks

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
Reference Clock (REFCLK0P/N, REFCLK1P/N)
F	Frequency		122.88		425	MHz
FHS_offset	Accuracy	Relative to Nominal HS Serial Data Rate	–100		100	ppm
FHS_offset	Accuracy	Relative to Incoming HS Serial Data Rate	–200		200	ppm
DC	Duty cycle	High Time	45%	50%	55%
V_ID	Differential input voltage		250		2000	mV_pp
C_IN	Input capacitance				1	pF
R_IN	Differential input impedance			100		Ω
t_RISE	Rise/fall time	10% to 90%	50		350	ps
Differential Output Clock (CLKOUTA/N)
F	Output frequency		0		500	MHz
V_OD	Differential output voltage	Peak to peak	1000		2000	mV_dfpp
t_RISE	Output rise time	10% to 90%, 2pF lumped capacitive load, AC-Coupled			350	ps
R_TERM	Output termination	CLKOUTAP/N × P/N to DVDD		50		Ω

5.11 Timing Requirements

over recommended operating conditions (unless otherwise noted)

		TEST CONDITIONS	MIN	MAX	UNIT
MDIO
t_period	MDC period	See Figure 6-3	100		ns
t_setup	MDIO setup to ↑ MDC		10		ns
t_hold	MDIO hold to ↑ MDC		10		ns
t_valid	MDIO valid from MDC ↑		0	40	ns
JTAG
t_period	TCK period	See Figure 6-4	66.67		ns
t_setup	TDI/TMS/TRST_N setup to ↑ TCK		3		ns
t_hold	TDI/TMS/TRST_N hold from ↑ TCK		5		ns
t_valid	TDO delay from TCK Falling		0	10	ns

5.12 Typical Characteristics

Figure 5-1 10GBASE-KR Fitted Channel Attenuation Limit

Figure 5-2 Eye Diagram of the TLK10031 at 10.3125 Gbps Under Nominal Conditions