ZHCSIC6A June   2018  – January 2019 TLC6946 , TLC6948

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      T48 路多路复用 LC6948典型应用原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Pin Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Built-In 16Kb Display Memory (SRAM)
      2. 9.3.2  GCLK Dual-Edge Operation
      3. 9.3.3  Programmable Constant-Sink Channel Current
        1. 9.3.3.1 Global Brightness Control (BC)
        2. 9.3.3.2 Select RIREF for a Given BC
      4. 9.3.4  Grayscale (GS) Function (PWM Control)
      5. 9.3.5  Serial Data Interface
      6. 9.3.6  LED-Open Detection (LOD)
      7. 9.3.7  Caterpillar Removal
      8. 9.3.8  Precharge FET
      9. 9.3.9  Thermal Shutdown
      10. 9.3.10 IREF Resistor Short Protection (ISP)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operating Mode
      2. 9.4.2 Power-Save Mode (PSM)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Power Supply Voltage
        2. 10.2.2.2 Channel Current and Brightness Control
        3. 10.2.2.3 SCLK and GCLK Frequency
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

12.1 Layout Guidelines

Place the decoupling capacitor near the VCC pin and GND plane.

Place the current-programming resistor, RIREF, close to the IREF pin and the GND pin.

Make the GND trace as wide as possible for large GND currents.

Routing between the LED cathode and the device OUTn pin must be as short and straight as possible to reduce wire inductance.

The thermal pad (QFN package) must be connected to the GND plane. Because the thermal pad is used as a power ground pin internally, there is a large current flow through this pad when all channels turn on. Furthermore, connect the thermal pad to a heat sink layer by thermal vias to reduce device temperature. One suggested thermal via pattern is shown in Layout Examples. For more information about suggested thermal via pattern and via size, see PowerPAD Thermally Enhanced Package.

MOSFETs must be placed in the in the middle of the board, which should be laid out as symmetrically as possible.