SLLS228G December   1995  – August 2015 TIR1000

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 IrDA Encoder Function
      2. 7.4.2 IrDA Decoder Function
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

There is no fundamental information about how many layers should be used and how the board stackup should look. Again, the easiest way the get good results is to use the design from the EVMs of Texas Instruments. The magazine Elektronik Praxis

(1) Elektronik-Praxis: Die Leiterplatte 2010, Ausgabe 11/06, P72-77
has published an article with an analysis of different board stackups. These are listed in Table 3. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a GND plane. Better is the use of a four-layer PCB, with a GND and a VCC plane and two signal layers. If the circuit is complex and signals must be routed as stripline, because of propagation delay and/or characteristic impedance, a six-layer stackup should be used.

Table 3. Possible Board Stackup on a Four-Layer PCB

MODEL 1 MODEL 2 MODEL 3 MODEL 4
Layer 1 SIG SIG SIG GND
Layer 2 SIG GND GND SIG
Layer 3 VCC VCC SIG VCC
Layer 4 GND SIG VCC SIG
Decoupling Good Good Bad Bad
EMC Bad Bad Bad Bad
Signal integrity Bad Bad Good Bad
Self disturbance Satisfaction Satisfaction Satisfaction High

Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any impedance change, the best routing would be a round bend as shown in Figure 13.

TIR1000 TIR1000I Layout_SLLS228.gifFigure 13. Poor and Good Right Angle Bends

10.2 Layout Example

TIR1000 TIR1000I layout_ex_slls228.gifFigure 14. Layout Example