SLES032E Data sheet | 德州仪器 TI.com.cn

SLES032E June 2002 – September 2014 THS8200

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PFP|80
- MPQF049B

散热焊盘机械数据 (封装 | 引脚)

PFP|80
- PPTD014N

订购信息

3 Terminal Configuration and Functions

Figure 3-1 shows the pinout for the PFP package.

Figure 3-1 80-Pin PFP Package (Top View)

3.1 Terminal Functions

Table 3-1 describes the signals for the device.

Table 3-1 Terminal Functions

TERMINAL		I/O ⁽¹⁾	DESCRIPTION
NAME	NO.	I/O ⁽¹⁾	DESCRIPTION
ABPb	15	O	Analog output of DAC2. See AGY.
ARPr	17	O	Analog output of DAC3. See AGY.
AGY	13	O	Analog output of DAC1. With the proper setting of FSADJ<n>, this output is capable of driving 1.3-V full scale into a 37.5-Ω load.
AVDD	11, 14, 18	PWR	Analog power supply, nominal 3.3 V
AVSS	12, 16	PWR	Analog ground
BCb[9:0]	21 - 30	I	10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video data source. In 30-bit mode, the B data of RGB, or the Cb data of YCbCr, should be connected to this port. In 10-bit input mode, this port is unused. In 20-bit input mode, this port is used for CbCr input data.
CLKIN	3	I	Main clock input. Video input data on the GY[9:0]/BCb[9:0]/RCr[9:0] ports should be synchronized to CLKIN. Depending on the input data format, CLKIN is supplied to THS8200 at 1x or 2x the pixel clock frequency.
COMP1	10	P	Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected between COMP1 and analog power supply AVDD.
COMP2	9	P	Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected between COMP2 and analog power supply AVDD.
D1CLKO	71	O	Video ITU-R.BT656-compliant clock output. This clock output is off by default and should be activated by an I²C register setting.
DO[9:5] DO[4:0]	65-69 73-77	O	ITU-R.BT656 compliant video data output port. Only available when ITU-R.BT656 input format is used. Can be used to connect to external PAL/NTSC video encoder. This port is off by default and should be activated by an I²C register setting.
DVDD	32, 59, 79	PWR	Digital core power, nominal 1.8 V
DVSS	31, 58, 78	PWR	Digital core ground
FID	47	I	Field identification signal for interlaced video formats. In slave timing mode, this is an input from the video data source. In master timing mode this signal is unused, as only progressive-scan VESA formats are supported in master mode.
FSADJ1	7	P	Full scale adjustment control 1. A resistor should be connected between FSADJ1 and analog ground AGND to control the full-scale output current of the DAC output channels. The data_fsadj I²C programming register can be used to select between two full-scale ranges, determined by FSADJ1 or FSADJ2. For 700-mV video output (1 Vpp including sync), the nominal value is 2.99 kΩ ; for 1.0-Vpp video output (1.3 Vpp including sync) output the nominal value is 2.08 kΩ.
FSADJ2	8	P	Full scale adjustment control 2. See FSADJ1.
GND_DLL	2	PWR	Ground of clock doubler. Should be connected to analog ground.
GND_IO	20, 45, 72	PWR	I/O ring ground
GY[9:0]	48-57	I	10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video data source. The G data of RGB or the Y data of YCbCr should be connected to this port. Port used in 10-bit mode for CbYCrY video input data; in 20-bit input mode for Y data.
HS_IN	43	I/O	Horizontal source synchronization. In slave timing mode, this is an input from the video data source. In master timing mode, this is an output to the video data source with programmable timing and polarity, serving as a horizontal data qualification signal to the video source.
HS_OUT	61	O	Horizontal sync output (to display). Irrespective of slave/master timing mode configuration, this is always an output with timing generated by the DTG.
I2CA	5	I	I²C device address LSB selection
N.C.	1, 80	I	Manufacturing test input. Must be tied to GND for normal operation.
PBKG (VSS)	6	PWR	Substrate ground. Should be connected to analog ground.
RCr[9:0]	33-42	I	10-bit video data input port. All 10-bits or the 8 MSB of this port can be connected to the video data source. In 30-bit mode, the R data of RGB or the Cr data of YCbCr should be connected to this port. In the 10- /20-bit input mode, this port is unused. For some input formats this port is unused.
RESETB	60	I	Software reset pin (active low). The minimum reset duration is 200 ns.
SCL	64	B	Serial clock line of I²C bus interface. Open-collector. Maximum specified clock speed is 400 kHz (fast I²C).
SDA	63	B	Serial data line of I²C bus interface. Open-collector.
VDD_DLL	4	PWR	Power supply of clock doubler, 1.8 V nominal
VDD_IO	19, 46, 70	PWR	I/O ring power, 1.8 V or 3.3 V nominal
VS_IN	44	I/O	Vertical source synchronization. In slave timing mode, this is an input from the video data source. In master timing mode, this is an output to the video data source with programmable timing and polarity, serving as a vertical data qualification signal to the video source.
VS_OUT	62	O	Vertical sync output (to display). Regardless of slave/master timing mode configuration, this is always an output with timing generated by the DTG.

(1) I = input, O = output, B = bidirectional, PWR = power or ground, P = passive