ZHCSDZ2A February   2013  – July 2015 THS4532

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Related Products
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 2.7 V
    6. 7.6 Electrical Characteristics: VS = 5 V
    7. 7.7 Typical Characteristics
      1. 7.7.1 Typical Characteristics: VS = 2.7 V
      2. 7.7.2 Typical Characteristics: VS = 5 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
        1. 8.3.1.1 Setting the Output Common-Mode Voltage
      2. 8.3.2 Power Down
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Frequency Response and Output Impedance
      2. 9.1.2  Distortion
      3. 9.1.3  Slew Rate, Transient Response, Settling Time, Overdrive, Output Voltage, and Turnon and Turnoff Time
      4. 9.1.4  Common-Mode and Power Supply Rejection
      5. 9.1.5  VOCM Input
      6. 9.1.6  Balance Error
      7. 9.1.7  Single-Supply Operation
      8. 9.1.8  Low-Power Applications and the Effects of Resistor Values on Bandwidth
      9. 9.1.9  Driving Capacitive Loads
      10. 9.1.10 Audio Performance
      11. 9.1.11 Audio On and Off Pop Performance
    2. 9.2 Typical Applications
      1. 9.2.1 SAR ADC Performance: THS5432 and ADS8321 Combined Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Audio ADC Driver Performance: THS5432 and PCM4204 Combined Performance
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 SAR ADC Performance: THS5432 and ADS7945 Combined Performance
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
    3. 9.3 Systems Examples
      1. 9.3.1 Differential-Input to Differential-Output Amplifier
        1. 9.3.1.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
      2. 9.3.2 Single-Ended to Differential FDA Configuration
        1. 9.3.2.1 Input Impedance
      3. 9.3.3 Single-Ended Input to Differential Output Amplifier
        1. 9.3.3.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.3.3.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.3.3.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
      4. 9.3.4 Differential Input to Single-Ended Output Amplifier
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 72 shows the general test circuit built on the EVM that was used for testing the THS5432. For simplicity, power supply decoupling is not shown – see Layout for recommendations. Depending on the test conditions, component values are changed per Table 4 and Table 5, or as otherwise noted. Some of the signal generators used are AC-coupled 50-Ω sources and a 0.22-µF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the un-driven or alternate input as shown to balance the circuit. A split-power supply is used to ease the interface to common lab test equipment, but if properly biased, the amplifier can be operated single-supply as described in the applications section with no impact on performance. For most of the tests, the devices are tested with single ended input and a transformer on the output to convert the differential output to single ended because common lab test equipment have single ended inputs and outputs. Performance is the same or better with differential input and differential output.

THS4532 General_Test_Circuit_los829.gifFigure 72. General Test Circuit

Table 4. Gain Component Values for Single-Ended Input(1)

GAIN RF RG RIT
1 V/V 2 kΩ 2 kΩ 51.1 Ω
2 V/V 2 kΩ 1 kΩ 52.3 Ω
5 V/V 2 kΩ 392 Ω 53.6 Ω
10 V/V 2 kΩ 187 Ω 57.6 Ω
(1) Components are chosen to achieve gain and 50-Ω input termination. Resistor values shown are closest standard values so gains are approximate.

Table 5. Load Component Values For 1:1 Differential to Single-Ended Output Transformer(1)

RL RO ROT ATTEN (dB)
100 Ω 25 Ω open 6
200 Ω 84.5 Ω 71.5 Ω 16.7
500 Ω 237 Ω 56.2 Ω 25.6
1 kΩ 487 Ω 52.3 Ω 31.8
2 kΩ 976 Ω 51.1 Ω 38
(1) The total load includes 50-Ω termination by the test equipment. Components are chosen to achieve load and 50-Ω line termination through a 1:1 transformer. Resistor values shown are closest standard values so loads are approximate.

Because of the voltage divider on the output formed by the load component values, the output of the amplifier is attenuated. The column ATTEN in Table 5 shows the attenuation expected from the resistor divider. When using a transformer at the output as shown in Figure 72, the signal has slightly more loss because of transformer insertion loss, and these numbers are approximate. The standard output load used for most tests is 2 kΩ with associated 38 dB of loss.

9.1.1 Frequency Response and Output Impedance

The circuit shown in Figure 72 is used to measure the frequency response of the amplifier.

A network analyzer is used as the signal source and the measurement device. The output impedance of the network analyzer is 50 Ω and is AC coupled. RIT and RG are selected to impedance match to 50 Ω and maintain the proper gain. To balance the amplifier, a 49.9-Ω resistor and blocking capacitor to ground is inserted across RIT on the alternate input.

The output is routed to the input of the network analyzer through 50-Ω coax. For a 2k load, 38 dB is added to the measurement to refer back to the output of the amplifier according to Table 5.

For output impedance, the signal is injected at VOUT with VIN left open. The voltage drop across the 2x RO resistors is measured with a high impedance differential probe and used to calculate the impedance into the output of the amplifier.

9.1.2 Distortion

At 1 MHz and above, the circuit shown in Figure 72 is used to measure harmonic, intermodulation distortion, and output impedance of the amplifier.

A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output impedance of the signal generator is 50 Ω and is AC coupled. RIT and RG are chosen to impedance match to 50 Ω and maintain the proper gain. To balance the amplifier, a 0.22-µF capacitor and 49.9-Ω resistor to ground is inserted across RIT on the alternate input. A low-pass filter is inserted in series with the input to reduce harmonics generated by the signal source. The level of the fundamental is measured and then a high-pass filter is inserted at the output to reduce the fundamental so it does not generate distortion in the input of the spectrum analyzer.

Distortion in the audio band is measured using an audio analyzer. Refer to the Audio Performance section for details.

9.1.3 Slew Rate, Transient Response, Settling Time, Overdrive, Output Voltage, and Turnon and Turnoff Time

The circuit shown in Figure 73 is used to measure slew rate, transient response, settling time, overdrive recovery, and output voltage swing. Turnon and turnoff times are measured with 50-Ω input termination on the PD input, by replacing the 0.22-µF capacitor with 49.9-Ω resistor.

THS4532 SR_Trans_settle_t_Zo_Ovr_drv_Vo_Turn_on_off_los829.gifFigure 73. Slew Rate, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, and Turn-On and Turn-Off Test Circuit

9.1.4 Common-Mode and Power Supply Rejection

The circuit shown in Figure 74 is used to measure the CMRR. The signal from the network analyzer is applied common-mode to the input.

THS4532 CMRR_Test_Circuit_los829.gifFigure 74. CMRR Test Circuit

Figure 75 is used to measure the PSRR of VS+ and VS-. The power supply is applied to the network DC offset input of the analyzer. For both CMRR and PSRR, the output is probed using a high impedance differential probe across ROT. The calculated CMRR and PSRR are referred to the input of the device.

THS4532 PSRR_Test_Circuit_los829.gifFigure 75. PSRR Test Circuit

9.1.5 VOCM Input

The circuit shown in Figure 76 is used to measure the transient response, frequency response, and input impedance of the VOCM input. For these tests, the cal point is across the 49.9 Ω VOCM termination resistor. Transient response and frequency response are measured with RCM = 0 Ω and using a high impedance differential probe at the summing junction of the two RO resistors, with respect to ground. The input impedance is measured using a high impedance differential probe at the VOCM pin and the drop across RCM is used to calculate the impedance into the VOCM input of the amplifier.

THS4532 Vocm_input_Test_Circuit_los829.gifFigure 76. VOCM Input Test Circuit

9.1.6 Balance Error

The circuit shown in Figure 77 is used to measure the balance error of the main differential amplifier. A network analyzer is used as the signal source and the measurement device. The output impedance of the network analyzer is 50 Ω and is DC coupled. RIT and RG are chosen to impedance match to 50 Ω and maintain the proper gain. To balance the amplifier, a 49.9-Ω resistor to ground is inserted across RIT on the alternate input. The output is measured using a high impedance differential probe at the summing junction of the two RO resistors, with respect to ground.

THS4532 Balance_Error_los829.gifFigure 77. Balance Error Test Circuit

9.1.7 Single-Supply Operation

To facilitate testing with common lab equipment, the THS5432 EVM is built to allow for split-supply operation and most of the data presented in this data sheet was taken with split-supply power inputs. The device is designed for use with single-supply power operation and can easily be used with single-supply power without degrading the performance. The only requirement is to bias the device properly and the specifications in this data sheet are given for single supply operation.

9.1.8 Low-Power Applications and the Effects of Resistor Values on Bandwidth

The THS5432 is designed for the nominal value of RF to be 2 kΩ. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. It also loads the amplifier. For example; in gain of 1 with RF = RG = 2 kΩ, RG to ground, and VOUT+ = 4 V, 1 mA of current will flow through the feedback path to ground. In low power applications, reducing this current is desirable by increasing the gain setting resistors values. Using larger value gain resistors has three primary side effects (other than lower power) because of the interaction with the device and PCB parasitic capacitance:

  • Lowers the bandwidth.
  • Lowers the phase margin.
    • This causes peaking in the frequency response.
    • This also causes overshoot and ringing in the pulse response.
  • Increases the output noise.

Figure 78 shows the small signal frequency response for gain of 1 with RF and RG equal to 2 kΩ, 10 kΩ, and 100 kΩ. The test was done with RL = 2 kΩ. Because of loading effects of RL, lower values may reduce the peaking, but higher values will not have a significant effect.

As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in frequency response is synonymous with overshoot and ringing in pulse response). These effects are caused by the feedback pole created by the summing-junction capacitance and these larger Rf values.

THS4532 G067_Gain_vs_Freq_RF.pngFigure 78. THS5432 Frequency Response with Various Gain Setting Resistor Values

9.1.9 Driving Capacitive Loads

The THS5432 is designed for a nominal parasitic capacitive load of 2 pF (differentially). When driving capacitive loads greater than this, TI recommends using small resisters (RO) in series with the output as close to the device as possible. Without RO, capacitance on the output interacts with the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that reduces the phase margin resulting in:

  • Peaking in the frequency response.
  • Overshoot, undershoot, and ringing in the time domain response with a pulse or square-wave signal.
  • May lead to instability or oscillation.

Inserting RO compensates the phase shift and restores the phase margin, but it also limits bandwidth. The circuit shown in Figure 73 is used to test for best RO versus capacitive loads, CL, with a capacitance placed differential across the VOUT+ and VOUT- along with 2-kΩ load resistor, and the output is measure with a differential probe. Figure 79 shows the suggested values of RO versus capacitive loads, CL, and Figure 80 shows the frequency response with various values. Performance is the same on both 2.7-V and 5-V supply.

THS4532 G068_RO_vs_CLOAD.pngFigure 79. Recommended Series Output Resistor vs Capacitive Load for Flat Frequency Response
THS4532 G069_Gain_vs_Freq_CLOAD.pngFigure 80. Frequency Response for Various RO and CL Values

9.1.10 Audio Performance

The THS5432 provides excellent audio performance with very low quiescent power. To show performance in the audio band, the device was tested with an audio analyzer. THD+N and FFT tests were run at 1-Vrms output voltage. Performance is the same on both 2.7-V and 5-V supply. Figure 81 is the test circuit used, and Figure 82 and Figure 83 show performance of the analyzer. In the FFT plot the harmonic spurs are at the testing limit of the analyzer, which means the THS5432 is actually much better than can be directly measured. Because the THS5432 distortion performance cannot be directly measured in the audio band it is estimated from measurement in high noise gain configuration correlated with simulation.

THS4532 Audio_Analyzer_Test_Circuit_los829.gifFigure 81. THS5432 Audio Analyzer Test Circuit
THS4532 G070_THD_N_10Hz-24kHz.pngFigure 82. THD+N on Audio Analyzer, 10 Hz to 24 kHz
THS4532 G071_FFT_1kHz.pngFigure 83. 1-kHz FFT Plot on Audio Analyzer

9.1.11 Audio On and Off Pop Performance

The THS5432 is tested to show on and off pop performance by connecting a speaker between the differential outputs and switching on and off the power supply, and also by using the power down function of the THS5432. Testing was done with and without tones. During these tests no audible pop could be heard.

With no input tone, Figure 84 shows the voltage waveforms when switching power on to the THS5432 and Figure 85 shows voltage waveforms when turning power off. The transients during power on and off show no audible pop should be heard.

THS4532 G072_Power_Supply_Turn_On Pop_Performance.pngFigure 84. Power Supply Turnon Pop Performance
THS4532 G073_Power_Supply_Turn_Off_Pop_Performance.pngFigure 85. Power Supply Turnoff Pop Performance

With no input tone, Figure 86 shows the voltage waveforms using the PD pin to enable and disable the THS5432. The transients during power on and off show no audible pop should be heard.

THS4532 G074_PD_Enable_Pop_Performance.pngFigure 86. PD Enable Pop Performance

9.2 Typical Applications

The following circuits show application information for the THS5432. For simplicity, power-supply decoupling capacitors are not shown in these diagrams; see the Layout Guidelines section for suggested guidelines. For more details on the use and operation of fully-differential amplifiers, refer to the Application Report Fully-Differential Amplifiers (SLOA054), available for download from the TI website at www.ti.com.

9.2.1 SAR ADC Performance: THS5432 and ADS8321 Combined Performance

THS4532 THS5432_to_ADS8321_Test_Circuit_los829.gifFigure 87. THS5432 and ADS8321 Test Circuit

9.2.1.1 Design Requirements

To show achievable performance with a high performance SAR ADC, the THS5432 is tested as the drive amplifier for the ADS8321. The ADS8321 is a 16-bit, SAR ADC that offers excellent AC and DC performance, with ultra-low power and small size. The circuit shown in Figure 87 is used to test the performance. Data was taken using the ADS8321 at 100 kSPS with input frequency of 10 kHz and signal levels 0.5 dB below full scale. The FFT plot of the spectral performance is in Figure 88. A summary of the FFT analysis results are in Table 6 along with ADS8321 typical data sheet performance at fS = 100 kSPS. Refer to its data sheet for more information.

9.2.1.2 Detailed Design Procedure

The standard ADS8321 EVM and THS5432 EVM are modified to implement the schematic in Figure 87 and used to test the performance of the THS5432 as a drive amplifier. With single supply +5-V supply the output common-mode of the THS5432 defaults to +2.5 V as required at the input of the ADS8321 so the VOCM input of the THS5432 simply bypassed to GND with 0.22-µF capacitor. The summary of results of the FFT analysis versus typical data sheet performance shown in Table 6 show that the THS5432 will make an excellent drive amplifier for this ADC.

9.2.1.3 Application Curve

THS4532 G078_THS4531_to_ADS8321_10kHz_FFT.pngFigure 88. THS5432 + ADS8321 1-kHz FFT

Table 6. 10-kHz FFT Analysis Summary

CONFIGURATION TONE SIGNAL SNR THD SINAD SFDR
THS5432 + ADS8321 10 kHz –0.5 dBFS 87 dBc –96 dBc 87 dBc 100 dBc
ADS8321 Data Sheet (typical) 10 kHz –0.5 dBFS 87 dBc –86 dBc 84 dBc 86 dBc

9.2.2 Audio ADC Driver Performance: THS5432 and PCM4204 Combined Performance

THS4532 THS5432_and_PCM4204_Test_Circuit_los829.gifFigure 89. THS5432 and PCM4204 Test Circuit

9.2.2.1 Design Requirements

To show achievable performance with a high performance audio ADC, the THS5432 is tested as the drive amplifier for the PCM4204. The PCM4204 is a high-performance, four-channel analog-to-digital converter (ADC) designed for professional and broadcast audio applications. The PCM4204 architecture uses a 1-bit delta-sigma modulator per channel incorporating an advanced dither scheme for improved dynamic performance, and supports PCM output data. The PCM4204 provides flexible serial port interface and many other advanced features. Refer to the PCM4204 data sheet for more information. Figure 89 shows the circuit.

9.2.2.2 Detailed Design Procedure

The PCM4204 EVM is used to test the audio performance of the THS5432 as a drive amplifier. The standard PCM4204 EVM is provided with 4x OPA1632 fully-differential amplifiers, which use the same pin out as the THS5432. For testing, one of these amplifiers is replaced with a THS5432 device in same package (MSOP), gain changed to 1 V/V, and power supply changed to single supply 5 V. With single supply +5-V supply the output common-mode of the THS5432 defaults to 2.5 V as required at the input of the PCM4204. So the resistor connecting the VOCM input of the THS5432 to the input common-mode drive from the PCM4204 is optional and no performance change was noted with it connected or removed. The EVM power connections were modified by connecting positive supply inputs, 15 V, 5 VA, and 5 VD, to a 5-V external power supply (EXT 3.3 was not used) and connecting –15 V and all ground inputs to ground on the external power supply so only one external 5-V supply was needed to power all devices on the EVM.

An audio analyzer is used to provide an analog audio input to the EVM and the PCM formatted digital output is read by the digital input on the analyzer. Data was taken at fS = 96 kHz, and audio output uses PCM format. Other data rates and formats are expected to show similar performance in line with that shown in the data sheet.

9.2.2.3 Application Curves

Figure 90 shows the THD+N vs Frequency with no weighting and Figure 91 shows an FFT with 1-kHz input tone. Input signal to the PCM4204 for these tests is –0.5 dBFS. Table 7 summarizes results of testing using the THS5432 + PCM4204 versus typical Data Sheet performance, and show it make an excellent drive amplifier for this ADC.

THS4532 G075_THD_N_DualRate.pngFigure 90. THS5432 + PCM4204 THD+N vs Frequency With No Weighting
THS4532 G076_FFT_1kHz_DualRate.pngFigure 91. THS5432 + PCM4204 1-kHz FFT

Table 7. 1-kHz AC Analysis: Test Circuit versus PCM4204 Data Sheet
Typical Specifications (fS = 96 kSPS)

CONFIGURATION TONE THD + N
THS5432 + PCM4204 1 kHz –106 dB
PCM4204 Data Sheet (typical) 1 kHz –103 dB

9.2.3 SAR ADC Performance: THS5432 and ADS7945 Combined Performance

THS4532 THS4532_to_ADS7945_Test_Circuit_los829.gifFigure 92. THS5432 and ADS7945 Test Circuit

9.2.3.1 Design Requirements

To show achievable performance with a high performance SAR ADC, the THS5432 is tested as the drive amplifier for the ADS7945. The ADS7945 is a 14-bit, SAR ADC that offers excellent AC and DC performance, with low power and small size. The circuit shown in Figure 92 is used to test the performance. Data was taken using the ADS7945 at 2MSPS with input frequency of 10 kHz and signal level 0.5 dB below full scale. The FFT plot of the spectral performance is in Figure 93. A summary of the FFT analysis results are in Table 8 along with ADS7945 typical data sheet performance at fS = 2 MSPS. Refer to the data sheet for more information.

9.2.3.2 Detailed Design Procedure

The standard ADS7945 EVM and THS5432 EVM are modified to implement the schematic in Figure 92 and used to test the performance of the THS5432 as a drive amplifier. With single supply 5 V supply the output common-mode of the THS5432 defaults to +2.5 V as required at the input of the ADS7945 so the VOCM input of the THS5432 simply bypassed to GND with 0.22-µF capacitor. The summary of results of the FFT analysis versus typical data sheet performance shown in Table 8 show that the THS5432 will make an excellent drive amplifier for this ADC.

9.2.3.3 Application Curve

THS4532 G077_THS4531_to_ADS7945_10kHz_FFT.pngFigure 93. THS5432 and ADS7945 Test Circuit

Table 8. 10-kHz FFT Analysis Summary

CONFIGURATION TONE SIGNAL SNR THD SFDR
THS5432 + ADS7945 10 kHz –0.5 dBFS 83 dBc –93 dBc 96 dBc
ADS7945 Data Sheet (typ) 10 kHz –0.5 dBFS 84 dBc –92 dBc 94 dBc

9.3 Systems Examples

9.3.1 Differential-Input to Differential-Output Amplifier

The THS5432 is a fully-differential amplifier and can be used to amplify differential input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 94 (VOCM and PD inputs not shown). The gain of the circuit is set by RF divided by RG.

THS4532 Diff_to_Diff_Amplifier_los829.gifFigure 94. Differential Input to Differential Output Amplifier

9.3.1.1 AC-Coupled, Differential-Input to Differential-Output Design Issues

There are two typical ways to use the THS5432 family with an AC-coupled differential source. In the first method, the source is differential and can be coupled in through two blocking capacitors. The second method uses either a single-ended or a differential source and couples in through a transformer (or balun). Figure 95 shows a typical blocking capacitor approach to a differential input. An optional differential-input termination resistor (RM) is included in this design. This RM element allows the input RG resistors to be scaled up while still delivering lower differential input impedance to the source. In this example, the RG elements sum to show a 500-Ω differential impedance, while the RM element combines in parallel to give a net 100-Ω, AC-coupled, differential impedance to the source. Again, the design proceeds ideally by selecting the RF element values, then the RG to set the differential gain, then an RM element (if needed) to achieve the target input impedance. Alternatively, the RM element can be eliminated, the RG elements set to the desired input impedance, and RF set to the get the differential gain (RF / RG).

THS4532 Example_Down_Converting_Mixer.gifFigure 95. Example Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the THS5432

The DC biasing here is very simple. The output VOCM is set by the input control voltage; and because there is no DC-current path for the output common-mode voltage, that DC bias also sets the input pins common-mode operating points.

9.3.2 Single-Ended to Differential FDA Configuration

9.3.2.1 Input Impedance

The designs so far have included a source impedance, RS, that must be matched by RT and RG1. The total impedance at the junction of RT and RG1 for the circuit of Figure 99 is the parallel combination of RT to ground, and the ZA (active impedance) presented by RG1. The expression for ZA, assuming RG2 is set to obtain the differential divider balance, is given by Equation 5:

Equation 5. THS4532 EQ5.gif

For designs that do not need impedance matching, for instance where the input is driven from the low-impedance output of another amplifier, RG1 = RG2 is the single-to-differential design used without an RT to ground. Setting RG1 = RG2 = RG in Equation 5 produces Equation 6, which is the input impedance of a simple-input FDA driven from a low-impedance, single-ended source.

Equation 6. THS4532 EQ6.gif

In this case, setting a target gain as RF / RG ≡ α, and then setting the desired input impedance allows the RG element to be resolved first. Then the RF is set to get the target gain. For example, targeting an input impedance of 200 Ω with a gain of 4 V/V, Equation 7 calculates the RG value. Multiplying this required RG value by a gain
of 4 gives the RF value and the design of Figure 96.

Equation 7. THS4532 EQ7.gif
THS4532 Ohm_Input_Impedance.gifFigure 96. 200-Ω Input Impedance, Single-Ended to Differential DC-Coupled Design With Gain of 4 V/V

After being designed, this circuit can also be AC-coupled by adding blocking caps in series with the two 120-Ω RG resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage using lower resistors values, leading to lower output noise for a given gain target.

9.3.3 Single-Ended Input to Differential Output Amplifier

The THS5432 can also be used to amplify and convert single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 97 (VOCM and PD inputs not shown). The gain of the circuit is again set by RF divided by RG.

THS4532 SE_to_Diff_Amplifier_los829.gifFigure 97. Single-Ended Input to Differential Output Amplifier

9.3.3.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion

When the signal path can be AC-coupled, the DC biasing for the THS5432 family becomes a relatively simple task. In all designs, start by defining the output common-mode voltage. The AC-coupling issue can be separated for the input and output sides of an FDA design. The input can be AC-coupled and the output DC-coupled, or the output can be ac-coupled and the input dc-coupled, or they can both be AC-coupled.

One situation where the output might be DC-coupled (for an AC-coupled input), is when driving directly into an ADC where the VOCM control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the required ADC input common-mode. In any case, the design starts by setting the desired VOCM.

When an AC-coupled path follows the output pins, the best linearity is achieved by operating VOCM at midsupply. The VOCM voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications (approximately 0.91 V greater than the negative supply and 1.1 V less than the positive supply). If the output path is also ac-coupled, simply letting the VOCM control pin float is usually preferred to get a midsupply default VOCM bias with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the VOCM pin to ground.

After VOCM is defined, check the target output voltage swing to ensure that the VOCM plus the positive and negative output swing on each side do not clip into the supplies. If the desired output differential swing is defined as VOPP, divide by 4 to obtain the ±VP swing around VOCM at each of the two output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed the absolute supply rails for this rail-to-rail output (RRO) device.

Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side are DC-blocked (see Figure 98), no common-mode current flows from the output common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage.

This input headroom also sets a limit for higher VOCM voltages. Because the input VICM is the output VOCM for ac-coupled sources, the 1.2-V minimum headroom for the input pins to the positive supply overrides the 1.1-V headroom limit for the output VOCM. Also, the input signal moves this input VICM around the dc bias point, as described in the section Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA.

THS4532 AC_coupled_single_ended_source_diff_gain.gifFigure 98. AC-Coupled, Single-Ended Source to a Differential Gain of 2 V/V Test Circuit

9.3.3.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion

The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled while the output is AC-coupled. A DC-coupled input with an AC-coupled output might have some advantages to move the input VICM down if the source is ground referenced. When the source is DC-coupled into the THS5432 family (see Figure 99), both sides of the input circuit must be DC-coupled to retain differential balance. Normally, the nonsignal input side has an RG element biased to whatever the source midrange is expected to be. Providing this midscale reference gives a balanced differential swing around VOCM at the outputs.

Often, RG2 is simply grounded for DC-coupled, bipolar-input applications. This configuration gives a balanced differential output if the source is swinging around ground. If the source swings from ground to some positive voltage, grounding RG2 gives a unipolar output differential swing from both outputs at VOCM (when the input is at ground) to one polarity of swing. Biasing RG2 to an expected midpoint for the input signal creates a differential output swing around VOCM.

One significant consideration for a DC-coupled input is that VOCM sets up a common-mode bias current from the output back through RF and RG to the source on both sides of the feedback. Without input balancing networks, the source must sink or source this DC current. After the input signal range and biasing on the other RG element is set, check that the voltage divider from VOCM to VIN through RF and RG (and possibly RS) establishes an input VICM at the device input pins that is in range.

If the average source is at ground, the negative rail input stage for the THS5432 family is in range for applications using a single positive supply and a positive output VOCM setting because this DC current lifts the average FDA input summing junctions up off of ground to a positive voltage (the average of the V+ and V– input pin voltages on the FDA).

THS4532 DC_Coupled_Single_Ended_to_Diff.gifFigure 99. DC-Coupled, Single-Ended-to-Differential, Set for a Gain of 5 V/V 

9.3.3.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA

The design equations for setting the resistors around an FDA to convert from a single-ended input signal to differential output can be approached from several directions. Here, several critical assumptions are made to simplify the results:

  • The feedback resistors are selected first and set equal on the two sides.
  • The DC and AC impedances from the summing junctions back to the signal source and ground (or a bias voltage on the nonsignal input side) are set equal to retain feedback divider balance on each side of the FDA.

Both of these assumptions are typical for delivering the best dynamic range through the FDA signal path.

After the feedback resistor values are chosen, the aim is to solve for the RT (a termination resistor to ground on the signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the nonsignal input side); see Figure 98 and Figure 99. The same resistor solutions can be applied to either AC- or DC-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. Adding these blocking capacitors after the RT element (as shown in Figure 98) has the advantage of removing any DC currents in the feedback path from the output VOCM to ground.

Earlier approaches to the solutions for RT and RG1 (when the input must be matched to a source impedance, RS) follow an iterative approach. This complexity arises from the active input impedance at the RG1 input. When the FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs must move with the input signal to generate the inverted output signal as a current in the RG2 element. A more recent solution is shown as Equation 8, where a quadratic in RT can be solved for an exact value. This quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only inputs required are:

  • The selected RF value.
  • The target voltage gain (Av) from the input of RT to the differential output voltage.
  • The desired input impedance at the junction of RT and RG1 to match RS.

Solving this quadratic for RT starts the solution sequence, as shown in Equation 8:

Equation 8. THS4532 EQ1.gif

Being a quadratic, there are limits to the range of solutions. Specifically, after RF and RS are chosen, there is physically a maximum gain beyond which Equation 8 starts to solve for negative RT values (if input matching is a requirement). With RF selected, use Equation 9 to verify that the maximum gain is greater than the desired gain.

Equation 9. THS4532 EQ2.gif

If the achievable AV(MAX) is less than desired, increase the RF value. After RT is derived from Equation 8, the RG1 element is given by Equation 10:

Equation 10. THS4532 EQ3.gif

Then, the simplest approach is to use a single RG2 = RT || RS + RG1 on the nonsignal input side. Often, this approach is shown as the separate RG1 and RS elements. Using these separate elements provides a better divider match on the two feedback paths, but a single RG2 is often acceptable. A direct solution for RG2 is given as Equation 11:

Equation 11. THS4532 EQ4.gif

This design proceeds from a target input impedance matched to RS, signal gain Av from the matched input to the differential output voltage, and a selected RF value. The nominal RF value chosen for the THS5432 family characterization is 2 kΩ. As discussed previously, going lower improves noise and phase margin, but reduces the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise, and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the total loading on the outputs.

Using Equation 9 to Equation 11 to sweep the target gain from 1 to AV(MAX) < 10 V/V gives Table 9, which shows exact values for RT, RG1, and RG2, where a 50-Ω source must be matched while setting the two feedback resistors to 2 kΩ. One possible solution for 1% standard values is shown, and the resulting actual input impedance and gain with % errors to the targets are also shown in Table 9.

Table 9. Rf = 2 kΩ, Matched Input to 50 Ω, Gain of 1 to 10-V/V Single-Ended to Differential(1)

Av Rt, EXACT (Ω) Rt 1% Rg1, EXACT (Ω) Rg1 1% Rg2, EXACT (Ω) Rg2 1% ACTUAL ZIN %ERR TO Rs ACTUAL GAIN %ERR TO Av
1 51 51.1 1996.5 2000 2021.8 2000 50.1 0.3 0.998 –0.2
2 51.7 52.3 996.9 1000 1022.5 1020 50.5 1.0 1.994 –0.3
3 52.5 52.3 656.1 649 681.7 681 49.7 –0.5 3.032 1.1
4 53.2 53.6 491.5 487 517.4 523 50.2 0.4 4.035 0.9
5 54 53.6 388 392 413.9 412 49.6 –0.9 4.953 –0.9
6 54.7 54.9 322.7 324 348.9 348 49.9 –0.2 5.978 –0.4
7 55.5 54.9 272.9 274 299.1 301 49.1 –1.7 6.974 –0.4
8 56.3 56.2 238.1 237 264.6 267 49.3 –1.3 8.034 0.4
9 57.1 57.6 211.2 210 237.9 237 49.7 –0.6 9.044 0.5
10 57.9 57.6 187.4 187 214.1 215 48.9 –2.3 10.017 0.2
(1) RF = 2 kΩ, RS = 50 Ω.

These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback resistors determines the frequency response flatness. Similar tables can be built using the equations provided here for other source impedances, RF values, and gain ranges.

The TINA model correctly shows this actively-set input impedance in the single-ended to differential configuration, and is a good tool to validate the gains, input impedances, response shapes, and noise issues.

9.3.4 Differential Input to Single-Ended Output Amplifier

Fully-differential amplifiers like the THS5432 are not recommended for differential to single-ended conversion. This application is best performed with an instrumentation amplifier or with a standard amplifier configured as a classic differential amplifier. See application section of the OPA835 data sheet (SLOS713).