SLVSLJ5 March   2026 TCA9846

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Electrical Characteristics (Global)
    6. 5.6 Thermal Information
    7. 5.7 I2C Interface Timing Requirements
    8. 5.8 Reset Timing Requirements
    9. 5.9 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET Input
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 Device Address
      3. 7.5.3 Bus Transactions
        1. 7.5.3.1 Writes
        2. 7.5.3.2 Reads
      4. 7.5.4 Control Register
      5. 7.5.5 RESET Input
      6. 7.5.6 Power-On Reset
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     Package Option Addendum
    2. 11.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics (Global)

T = 25C (unless otherwise noted)
PARAMETERTEST CONDITIONSTAMINTYPMAXUNIT
Recommended Supply Sequencing and Ramp Rates
(dV/dt)ffall rate of change of voltage –40°C to +125°C 0.12000ms
(dV/dt)rrise rate of change of voltage –40°C to +125°C 0.12000ms
td(rst)reset delay time –40°C to +125°C 10us
ΔVDD(gl)glitch supply voltage difference–40°C to +125°C1V
tw(gl)VDDsupply voltage glitch pulse width–40°C to +125°C10us
VPOR(trip)power-on reset trip voltageFalling VDD2 –40°C to +125°C 0.7V
Rising VDD2 –40°C to +125°C 1.5V
SCL/SDA
VIHLogic voltage high–40°C to +125°C0.7VDD13.6V
VILLogic voltage low–40°C to +125°C-0.5+0.3VDD1V
IOLLOW-level output currentVOL = 0.4V –40°C to +125°C 15mA
IILInput leakage currentVI = VDD or 0–40°C to +125°C-11uA
CINLogic input capacitanceVI = VSS; all channels disabled–40°C to +125°C1012pF
SEL Inputs: A0-A1, RESET
VIHLogic voltage high –40°C to +125°C 0.7VDD13.6V
VILLogic voltage low –40°C to +125°C -0.5+0.2VDD1V
IILInput leakage currentVI = VDD or 0–40°C to +125°C-11μA
CINLogic input capacitanceVI = VSS; all channels disabled–40°C to +125°C24pF
Pass Gate
RONON-state resistanceVDD1 = 0.8V; VDD2 ≥ 1.65V; Vi(sw) = 0.16V; IO = 3mA–40°C to +125°C1024
VDD1 = 0.65V; VDD2 ≥ 1.65V; Vi(sw) = 0.16V; IO = 3mA –40°C to +125°C1024
VDD1 = 1.2V; VDD2 ≥ 1.8V; Vi(sw) = 0.24V; IO = 6mA–40°C to +125°C718
VDD1 > 2V; VDD2 ≥ 2.5V; Vi(sw) = 0.4V; IO = 20mA–40°C to +125°C512
Io(sw)Switch Output CurrentVDD2 = 1.65V to 3.6V; Vi(sw) = VDD1 to 3.6V; Vo(sw) = VDD1 to 3.6V–40°C to +125°C0100μA
ILLeakage currentVI = VDD or GND–40°C to +125°C-1+1.5μA
COFFInput/Ouput CapacitanceVI = GND; all switches disables–40°C to +125°C35pF