ZHCSEZ2D
January 2014 – October 2021
TCA9539-Q1
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
6.7
RESET Timing Requirements
6.8
Switching Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
I/O Port
8.3.2
RESET Input
8.3.3
Interrupt ( INT) Output
8.4
Device Functional Modes
8.4.1
Power-On Reset
8.5
Programming
8.5.1
I2C Interface
8.6
Register Maps
8.6.1
Device Address
8.6.2
Control Register And Command Byte
8.6.3
Register Descriptions
8.6.3.1
Bus Transactions
8.6.3.1.1
Writes
8.6.3.1.2
Reads
9
Power Supply Recommendations
9.1
Power-On Reset Requirements
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
接收文档更新通知
11.3
支持资源
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
术语表
封装选项
机械数据 (封装 | 引脚)
PW|24
MPDS363A
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsez2d_oa
zhcsez2d_pm
8.2
Functional Block Diagram
Pin numbers shown are for PW package.
All I/Os are set to inputs at reset.
Figure 8-1
Logic Diagram (Positive Logic)
At power-on reset, all registers return to default values.
Figure 8-2
Simplified Schematic of P-Port I/Os