ZHCSEZ2D January   2014  – October 2021 TCA9539-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 RESET Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 RESET Input
      3. 8.3.3 Interrupt ( INT) Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register And Command Byte
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1 Bus Transactions
          1. 8.6.3.1.1 Writes
          2. 8.6.3.1.2 Reads
  9. Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Register Descriptions

The Input Port registers (registers 0 and 1) shown in Table 8-4 reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register is accessed next.

Table 8-4 Registers 0 And 1 (Input Port Registers)
BitI0.7I0.6I0.5I0.4I0.3I0.2I0.1I0.0
DefaultXXXXXXXX
BitI1.7I1.6I1.5I1.4I1.3I1.2I1.1I1.0
DefaultXXXXXXXX

The Output Port registers (registers 2 and 3) shown in Table 8-5 show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Table 8-5 Registers 2 And 3 (Output Port Registers)
BitO0.7O0.6O0.5O0.4O0.3O0.2O0.1O0.0
Default11111111
BitO1.7O1.6O1.5O1.4O1.3O1.2O1.1O1.0
Default11111111

The Polarity Inversion registers (registers 4 and 5) shown in Table 8-6 allow Polarity Inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Table 8-6 Registers 4 And 5 (Polarity Inversion Registers)
BitN0.7N0.6N0.5N0.4N0.3N0.2N0.1N0.0
Default00000000
BitN1.7N1.6N1.5N1.4N1.3N1.2N1.1N1.0
Default00000000

The Configuration registers (registers 6 and 7) shown in Table 8-7 configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

Table 8-7 Registers 6 And 7 (Configuration Registers)
BitC0.7C0.6C0.5C0.4C0.3C0.2C0.1C0.0
Default11111111
BitC1.7C1.6C1.5C1.4C1.3C1.2C1.1C1.0
Default11111111