ZHCSI92D May   2018  – November 2020 TAS5805M

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Mode
      2. 6.7.2 Bridge Tied Load (BTL) Configuration Curves with BD Mode
      3. 6.7.3 Bridge Tied Load (BTL) Configuration Curves with Ferrite Bead + Capacitor as the Output Filter
      4. 6.7.4 Parallel Bridge Tied Load (PBTL) Configuration with 1SPW Modulation
      5. 6.7.5 Parallel Bridge Tied Load (PBTL) Configuration with BD Modulation
  8. Parameter Measurement Information
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
        2. 7.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Low EMI Modes
        1. 7.4.3.1 Spread Spectrum
        2. 7.4.3.2 Channel to Channel Phase Shift
        3. 7.4.3.3 Multi-Devices PWM Phase Synchronization
      4. 7.4.4 Thermal Foldback
      5. 7.4.5 Device State Control
      6. 7.4.6 Device Modulation
        1. 7.4.6.1 BD Modulation
        2. 7.4.6.2 1SPW Modulation
        3. 7.4.6.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Slave Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ Coefficients Update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Overcurrent Shutdown (OCSD)
          2. 7.5.3.3.2 Speaker DC Protection
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Device Over Voltage/Under Voltage Protection
            1. 7.5.3.3.4.1 Over Voltage Protection
            2. 7.5.3.3.4.2 Under Voltage Protection
          5. 7.5.3.3.5 Clock Fault
    6. 7.6 Register Maps
      1. 7.6.1 CONTROL PORT Registers
  10. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bootstrap Capacitors
      2. 8.1.2 Inductor Selections
      3. 8.1.3 Power Supply Decoupling
      4. 8.1.4 Output EMI Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedures
          1. 8.2.1.2.1 Step 1: Hardware Integration
          2. 8.2.1.2.2 Step 2: Speaker Tuning
          3. 8.2.1.2.3 Step 3: Software Integration
        3. 8.2.1.3 Application Curves
          1. 8.2.1.3.1 Audio Performance
          2. 8.2.1.3.2 EN55022 Conducted Emissions Results with Ferrite Bead as output filter
          3. 8.2.1.3.3 EN55022 Radiated Emissions Results with Ferrite Bead as output filter
      2. 8.2.2 MONO (PBTL) Systems
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Advanced 2.1 System (Two TAS5805M Devices)
  11. Power Supply Recommendations
    1. 9.1 DVDD Supply
    2. 9.2 PVDD Supply
  12. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Guidelines for Audio Amplifiers
      2. 9.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 9.1.3 Optimizing Thermal Performance
        1. 9.1.3.1 Device, Copper, and Component Layout
        2. 9.1.3.2 Stencil Pattern
          1. 9.1.3.2.1 PCB footprint and Via Arrangement
          2. 9.1.3.2.2 Solder Stencil
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  14. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

CONTROL PORT Registers

Table 7-6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.

Table 7-6 CONTROL PORT Registers
OffsetAcronymRegister NameSection
1hRESET_CTRLRegister 1Go
2hDEVICE_CTRL_1Register 2Go
3hDEVICE_CTRL_2Register 3Go
FhI2C_PAGE_AUTO_INCRegister 15Go
28hSIG_CH_CTRLRegister 40Go
29hCLOCK_DET_CTRLRegister 41Go
30hSDOUT_SELRegister 48Go
31hI2S_CTRLRegister 49Go
33hSAP_CTRL1Register 51Go
34hSAP_CTRL2Register 52Go
35hSAP_CTRL3Register 53Go
37hFS_MONRegister 55Go
38hBCK_MONRegister 56Go
39hCLKDET_STATUSRegister 57Go
4ChDIG_VOL_CTRLRegister 76Go
4EhDIG_VOL_CTRL2Register 78Go
4FhDIG_VOL_CTRL3Register 79Go
50hAUTO_MUTE_CTRLRegister 80Go
51hAUTO_MUTE_TIMERegister 81Go
53hANA_CTRLRegister 83Go
54hAGAINRegister 84Go
5ChBQ_WR_CTRL1Register 92Go
5DhDAC_CTRLRegister 93Go
60hADR_PIN_CTRLRegister 96Go
61hADR_PIN_CONFIGRegister 97Go
66hDSP_MISCRegister 102Go
67hDIE_IDRegister 103Go
68hPOWER_STATERegister 104Go
69hAUTOMUTE_STATERegister 105Go
6AhPHASE_CTRLRegister 106Go
6BhSS_CTRL0Register 107Go
6ChSS_CTRL1Register 108Go
6DhSS_CTRL2Register 109Go
6EhSS_CTRL3Register 110Go
6FhSS_CTRL4Register 111Go
70hCHAN_FAULTRegister 112Go
71hGLOBAL_FAULT1Register 113Go
72hGLOBAL_FAULT2Register 114Go
73hOT WARNINGRegister 115Go
74hPIN_CONTROL1Register 116Go
75hPIN_CONTROL2Register 117Go
76hMISC_CONTROLRegister 118Go
78hFAULT_CLEARRegister 120Go

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.

Table 7-7 CONTROL PORT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in Figure 7-16 and described in Table 7-8.

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Figure 7-16 RESET_CTRL Register
76543210
RESERVEDRST_MODRESERVEDRST_REG
R/WWRW
Table 7-8 RESET_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4RST_MODW0

WRITE CLEAR BIT

Reset Modules

WRITE CLEAR BIT Reset full digital core This bit resets full digital signal chain (Include DSP and Control Port Registers). Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP.

0: Normal

1: Reset modules

3-1RESERVEDR000

This bit is reserved

0RST_CONTROL_REGW0

WRITE CLEAR BIT

Reset Registers

This bit resets the control port registers back to their initial values. The RAM content is not cleared.

0: Normal

1: Reset control port registers

7.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in Figure 7-17 and described in Table 7-9.

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Figure 7-17 DEVICE_CTRL_1 Register
76543210
RESERVEDFSW_SELRESERVEDDAMP_PBTLDAMP_MOD
R/WR/WR/WR/WR/W
Table 7-9 DEVICE_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-4FSW_SELR/W000SELECT FSW
000:768K
001:384K
011:480K
100:576K
010:Reserved
101:Reserved
110:Reserved
111:Reserved
3RESERVEDR/W0

This bit is reserved

2DAMP_PBTLR/W00: SET DAMP TO BTL MODE
1: SET DAMP TO PBTL MODE
1-0DAMP_MODR/W00

00:BD MODE

01:1SPW MODE

10:HYBRID MODE

7.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]

DEVICE_CTRL_2 is shown in Figure 7-18 and described in Table 7-10.

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Figure 7-18 DEVICE_CTRL_2 Register
76543210
RESERVEDDIS_DSPMUTERESERVEDCTRL_STATE
R/WR/WR/WR/WR/W
Table 7-10 DEVICE_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4DIS_DSPR/W1DSP reset
When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3MUTER/W0Mute Both Left /Right Channel
This bit issues soft mute request for the left/right channel. The volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2RESERVEDR/W0

This bit is reserved

1-0CTRL_STATER/W00Device state control register
00: Deep Sleep
01: Sleep
10: Hi-Z,
11: PLAY

7.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in Figure 7-19 and described in Table 7-11.

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Figure 7-19 I2C_PAGE_AUTO_INC Register
76543210
RESERVEDPAGE_AUTOINC_REGRESERVED
R/WR/WR/W
Table 7-11 I2C_PAGE_AUTO_INC Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3PAGE_AUTOINC_REGR/W0Page auto increment disable
Disable page auto increment mode. for non -zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
2-0RESERVEDR/W000

This bit is reserved

7.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in Figure 7-20 and described in Table 7-12.

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Figure 7-20 SIG_CH_CTRL Register
76543210
BCK_RATIO_CONFIGUREFS_MODE
R/WR/W
Table 7-12 SIG_CH_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-4BCK_RATIO_CONFIGURER/W0000These bits indicate the configured BCK ratio, the number of BCK clocks in one audio frame.
0011: 32FS
0101: 64FS
0111: 128FS
1001: 256FS
1011: 512FS
3-0FS_MODER/W0000FS Speed Mode These bits select the FS operation mode, which must be set according to the current audio sampling rate.
0000: Auto detection
0010: 8KHz
0100: 16KHz
0110: 32KHz
1000: 44.1KHz
1001: 48KHz
1010: 88.2KHz
1011: 96KHz
Others Reserved

7.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in Figure 7-21 and described in Table 7-13.

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Figure 7-21 CLOCK_DET_CTRL Register
76543210
RESERVEDDIS_DET_PLLDIS_DET_BCLK_RANGEDIS_DET_FSDIS_DET_BCLKDIS_DET_MISSRESERVEDRESERVED
R/WR/WR/WR/WR/WR/WR/WR/W
Table 7-13 CLOCK_DET_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6DIS_DET_PLLR/W0Ignore PLL overate Detection
This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error will be reported. When ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5DIS_DET_BCLK_RANGER/W0Ignore BCK Range Detection
This bit controls whether to ignore the BCK range detection. The BCK must be stable between 256KHz and 50MHz or an error will be reported. When ignored, a BCK range error will not cause a clock error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4DIS_DET_FSR/W0Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When ignored, FS error will not cause a clock error.But CLKDET_STATUS will report fs error.
0: Regard FS detection
1: Ignore FS detection
3DIS_DET_BCLKR/W0Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 512FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error.
0: Regard BCK detection
1: Ignore BCK detection
2DIS_DET_MISSR/W0Ignore BCK Missing Detection
This bit controls whether to ignore the BCK missing detection. When ignored an BCK missing will not cause a clock error.
0: Regard BCK missing detection
1: Ignore BCK missing detection
1RESERVEDR/W0

This bit is reserved

0RESERVEDR/W0

This bit is reserved

7.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]

SDOUT_SEL is shown in Figure 7-22 and described in Table 7-14.

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Figure 7-22 SDOUT_SEL Register
7 6 5 4 3 2 1 0
RESERVED SDOUT_SEL
R/W
Table 7-14 SDOUT_SEL Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED 0

This bit is reserved

0 SDOUT_SEL R 0

SDOUT Select. This bit selects what is being output as SDOUT pin.


0: SDOUT is the DSP output (post-processing)


1: SDOUT is the DSP input (pre-processing)

7.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in Figure 7-23 and described in Table 7-15.

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Figure 7-23 I2S_CTRL Register
76543210
RESERVEDBCK_INVRESERVEDRESERVEDRESERVED
R/WR/WR/WRRR/W
Table 7-15 I2S_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5BCK_INVR/W0BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode
4-0RESERVEDR/W00000

This bit is reserved

7.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in Figure 7-24 and described in Table 7-16.

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Figure 7-24 SAP_CTRL1 Register
76543210
I2S_SHIFT_MSBRESERVEDDATA_FORMATI2S_LRCLK_PULSEWORD_LENGTH
R/WR/WR/WR/WR/W
Table 7-16 SAP_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7I2S_SHIFT_MSBR/W0

I2S Shift MSB

6RESERVEDR/W0

This bit is reserved

5-4DATA_FORMATR/W00I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2I2S_LRCLK_PULSER/W00

01: lrclk pulse < 8 SCLK. If the high width of LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, these two bits need set to 01.

1-0WORD_LENGTHR/W10I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits

7.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in Figure 7-25 and described in Table 7-17.

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Figure 7-25 SAP_CTRL2 Register
76543210
I2S_SHIFT
R/W
Table 7-17 SAP_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-0I2S_SHIFTR/W00000000I2S Shift LSB
These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample.
000000000: offset = 0 BCK (no offset)
000000001: ofsset = 1 BCK
000000010: offset = 2 BCKs
and
111111111: offset = 512 BCKs

7.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in Figure 7-26 and described in Table 7-18.

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Figure 7-26 SAP_CTRL3 Register
76543210
RESERVEDLEFT_DAC_DPATHRESERVEDRIGHT_DAC_DPATH
R/WR/WR/WR/W
Table 7-18 SAP_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5-4LEFT_DAC_DPATHR/W01

Left DAC Data Path. These bits control the left channel audio data path connection.

00: Zero data (mute)

01: Left channel data

10: Right channel data

11: Reserved (do not set)

3-2RESERVEDR/W00

This bit is reserved

1-0RIGHT_DAC_DPATHR/W01

Right DAC Data Path. These bits control the right channel audio data path connection.

00: Zero data (mute)

01: Right channel data

10: Left channel data

11: Reserved (do not set)

7.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in Figure 7-27 and described in Table 7-19.

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Figure 7-27 FS_MON Register
76543210
RESERVEDBCLK_RATIO_HIGHFS
R/WRR
Table 7-19 FS_MON Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5-4BCLK_RATIO_HIGHR00

2 msbs of detected BCK ratio

3-0FSR0000These bits indicate the currently detected audio sampling rate.
0000: FS Error
0010: 8KHz
0100: 16KHz
0110: 32KHz
1000: Reserved
1001: 48KHz
1011: 96KHz
Others Reserved

7.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in Figure 7-28 and described in Table 7-20.

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Figure 7-28 BCK_MON Register
76543210
BCLK_RATIO_LOW
R
Table 7-20 BCK_MON Register Field Descriptions
BitFieldTypeResetDescription
7-0BCLK_RATIO_LOWR00000000

These bits indicate the currently detected BCK ratio, the number of BCK clocks in one audio frame.

BCK = 32 FS~512 FS

7.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in Figure 7-29 and described in Table 7-21.

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Figure 7-29 CLKDET_STATUS Register
76543210
RESERVEDDET_STATUS
R/WR
Table 7-21 CLKDET_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5DET_STATUSR0This bit indicates whether the BCLK is overrate or underrate
4DET_STATUSR0This bit indicates whether the PLL is overrate
3DET_STATUSR0This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
2DET_STATUSR0This bit indicates whether the BCK is missing or not.
1DET_STATUSR0This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-512FS to be valid.
0DET_STATUSR0In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid or not. In non auto detection mode(reg_fsmode!=0), Fs error indicates that configured fs is different with detected fs. Even FS Error Detection Ignore is set, this flag will be also asserted.

7.6.1.15 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL_CTL is shown in Figure 7-30 and described in Table 7-22.

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Figure 7-30 DIG_VOL_CTL Register
76543210
PGA
R/W
Table 7-22 DIG_VOL_CTR Register Field Descriptions
BitFieldTypeResetDescription
7-0PGAR/W00110000Digital Volume
These bits control both left and right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute

7.6.1.16 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL2 is shown in Figure 7-31 and described in Table 7-23.

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Figure 7-31 DIG_VOL_CTRL2 Register
76543210
PGA_RAMP_DOWN_SPEEDPGA_RAMP_DOWN_STEPPGA_RAMP_UP_SPEEDPGA_RAMP_UP_STEP
R/WR/WR/WR/W
Table 7-23 DIG_VOL_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-6PGA_RAMP_DOWN_SPEEDR/W00Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4PGA_RAMP_DOWN_STEPR/W11Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-2PGA_RAMP_UP_SPEEDR/W00Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
1-0PGA_RAMP_UP_STEPR/W11Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the volume is ramping up.
00: Increment by 4 dB for each updat
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update

7.6.1.17 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL3 is shown in Figure 7-32 and described in Table 7-24.

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Figure 7-32 DIG_VOL_CTRL3 Register
76543210
FAST_RAMP_DOWN_SPEEDFAST_RAMP_DOWN_STEPRESERVED
R/WR/WR/W
Table 7-24 DIG_VOL_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
7-6FAST_RAMP_DOWN_SPEEDR/W00Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4FAST_RAMP_DOWN_STEPR/W11Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0RESERVEDR/W0000

This bit is reserved

7.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]

AUTO_MUTE_CTRL is shown in Figure 7-33 and described in Table 7-25.

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Figure 7-33 AUTO_MUTE_CTRL Register
76543210
RESERVEDREG_AUTO_MUTE_CTRL
R/WR/W
Table 7-25 AUTO_MUTE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00000

This bit is reserved

2REG_AUTO_MUTE_CTRLR/W10: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are about to be auto muted
1REG_AUTO_MUTE_CTRLR/W10: Disable right channel auto mute
1: Enable right channel auto mute
0REG_AUTO_MUTE_CTRLR/W10: Disable left channel auto mute
1: Enable left channel auto mute bit2: .

7.6.1.19 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in Figure 7-34 and described in Table 7-26.

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Figure 7-34 AUTO_MUTE_TIME Register
76543210
RESERVEDAUTOMUTE_TIME_LEFTRESERVEDAUTOMUTE_TIME_RIGHT
R/WR/WR/WR/W
Table 7-26 AUTO_MUTE_TIME Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-4AUTOMUTE_TIME_LEFTR/W000Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3RESERVEDR/W0

This bit is reserved

2-0AUTOMUTE_TIME_RIGHTR/W000Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec

7.6.1.20 ANA_CTRL Register (Offset = 53h) [reset = 0x00]

ANA_CTRL is shown in Figure 7-35 and described in Table 7-27.

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Figure 7-35 ANA_CTRL Register
76543210
ANA_CTRL
R/W
Table 7-27 ANA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-5ANA_CTRLR/W00

Class-D bandwidth control.

00: 80kHz;

01: 100kHz;

10: 120kHz;

11: 175kHz.

With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance.

4-0RESERVEDR/W00000

These bits are reserved

7.6.1.21 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in Figure 7-36 and described in Table 7-28.

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Figure 7-36 AGAIN Register
76543210
RESERVEDANA_GAIN
R/WR/W
Table 7-28 AGAIN Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4-0ANA_GAINR/W00000Analog Gain Control , with 0.5dB one step
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001: -0.5db
11111: -15.5 dB

7.6.1.22 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]

BQ_WR_CTRL1 is shown in Figure 7-37 and described in Table 7-29.

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Figure 7-37 BQ_WR_CTRL1 Register
76543210
RESERVEDBQ_WR_FIRST_COEF
R/WR/W
Table 7-29 BQ_WR_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000000

This bit is reserved

0BQ_WR_FIRST_COEFR/W0

Indicate the first coefficient of a BQ is starting to write.

7.6.1.23 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]

DAC_CTRL is shown in Figure 7-38 and described in Table 7-30.

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Figure 7-38 DAC_CTRL Register
76543210
DAC_FREQUENCY_SELDAC_DITHER_ENDAC_DITHERDAC_CTRL_DEM_SEL
R/WR/WR/WR/W
Table 7-30 DAC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7DAC_FREQUENCY_SELR/W1

DAC Frequency Select

0: 6.144MHz

1: 3.072MHz

6-5DAC_DITHER_ENR/W11DITHER_EN,
00: disable both stage dither
01: enable main stage dither
10: enable second stage dither
11: enbale both stage dither
4-2DAC_DITHERR/W110Dither level
100: -2^-7
101: -2^-8
110: -2^-9
111: -2^-10
000: -2^-13
001: -2^-14
010: -2^-15
011: -2^-16
1-0DAC_CTRL_DEM_SELR/W00

00: Enable DEM

11: Disable DEM

7.6.1.24 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]

ADR_PIN_CTRL is shown in Figure 7-39 and described in Table 7-31.

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Figure 7-39 ADR_PIN_CTRL Register
76543210
RESERVEDADR_OE
R/W - 0x0
Table 7-31 ADR_PIN_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000000

This bit is reserved

0ADR_OER/W0

ADR Output Enable This bit sets the direction of the ADR pin

0: ADR is input

1: ADR is output

7.6.1.25 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]

ADR_PIN_CONFIG is shown in Figure 7-40 and described in Table 7-32.

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Figure 7-40 ADR_PIN_CONFIG Register
76543210
RESERVEDADR_PIN_CONFIG
R/W
Table 7-32 ADR_PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

These bits are reserved

4-0ADR_PIN_CONFIGR/W00000

00000: off (low)

00011: Auto mute flag (asserted when both L and R channels are auto muted)

00100: Auto mute flag for left channel 0101: Auto mute flag for right channel

00110: Clock invalid flag (clock error or clock missing)

00111: Reserved

01001: Reserved

01011: ADR as FAULTZ output

7.6.1.26 DSP_MISC Register (Offset = 66h) [reset = 0h]

DSP_MISC is shown in Figure 7-41 and described in Table 7-33.

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Figure 7-41 DSP_MISC Register
76543210
BYPASS_CONTROL
R/W
Table 7-33 DSP_MISC Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

These bits are reserved

3BYPASS CONTROLR/W0

1: Left and Right will have use unique coef 0->Right channel will share left channel coefficient

2BYPASS CONTROLR/W0

1: bypass 128 tap FIR

1BYPASS CONTROLR/W0

1: bypass DRC (Only bypass DRC in L/R channel)

0BYPASS CONTROLR/W0

1: bypass EQ (Only bypass EQs in L/R channel)

7.6.1.27 DIE_ID Register (Offset = 67h) [reset = 0h]

DIE_ID is shown in Figure 7-42 and described in Table 7-34.

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Figure 7-42 DIE_ID Register
7 6 5 4 3 2 1 0
DIE_ID
R-0h
Table 7-34 DIE_ID Register Field Descriptions
Bit Field Type Reset Description
7-0 DIE_ID R 0h

DIE ID

7.6.1.28 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in Figure 7-43 and described in Table 7-35.

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Figure 7-43 POWER_STATE Register
7 6 5 4 3 2 1 0
STATE_RPT
R
Table 7-35 POWER_STATE Register Field Descriptions
Bit Field Type Reset Description
7-0 STATE_RPT R 00000000

0: Deep sleep

1: Sleep

2: HIZ

3: Play

Others: reserved

7.6.1.29 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in Figure 7-44 and described in Table 7-36.

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Figure 7-44 AUTOMUTE_STATE Register
76543210
RESERVEDZERO_RIGHT_MONZERO_LEFT_MON
RRR
Table 7-36 AUTOMUTE_STATE Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR000000

This bit is reserved

1ZERO_RIGHT_MONR0

This bit indicates the auto mute status for right channel.

0: Not auto muted

1: Auto muted

0ZERO_LEFT_MONR0

This bit indicates the auto mute status for left channel.

0: Not auto muted

1: Auto muted

7.6.1.30 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]

PHASE_CTRL is shown in Figure 7-45 and described in Table 7-37.

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Figure 7-45 PHASE_CTR Register
76543210
RESERVEDRAMP_PHASE_SELPHASE_SYNC _SELPHASE_SYNC _EN
R/WR/WR/WR/W
Table 7-37 PHASE_CTR Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3-2RAMP_PHASE_SELR/W00

Select ramp clock phase when multi devices integrated in one system to reduce EMI and peak supply peak current, it is recomended set all devices the same RAMP frequency and same spread spectrum. it must be set before driving device into PLAY mode if this feature is needed.

00: phase 0

01: phase1

10: phase2

11: phase3

1I2S_SYNC_ENR/W0

Use I2S to synchronize output PWM phase

0: Disable

1: Enable

0PHASE_SYNC_ENR/W0

0: RAMP phase sync disable

1: RAMP phase sync enable

7.6.1.31 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

SS_CTRL0 is shown in Figure 7-46 and described in Table 7-38.

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Figure 7-46 SS_CTRL0 Register
76543210
RESERVEDRESERVEDSS_PRE_DIV_SELSS_MANUAL_MODERESERVEDSS_RDM_ENSS_TRI_EN
R/WR/WR/WR/WR/WR/WR/W
Table 7-38 SS_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6RESERVEDR/W0

This bit is reserved

5SS_PRE_DIV_SELR/W0

Select pll clock divide 2 as source clock in manual mode

4SS_MANUAL_MODER/W0

Set ramp ss controller to manual mode

3-2RESERVEDR/W0

This bit is reserved

1SS_RDM_ENR/W0

Random SS enable

0SS_TRI_ENR/W0

Triangle SS enable

7.6.1.32 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in Figure 7-47 and described in Table 7-39.

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Figure 7-47 SS_CTRL1 Register
76543210
RESERVEDSS_RDM_CTRLSS_TRI_CTRL
R/WR/WR/W
Table 7-39 SS_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-4SS_RDM_CTRLR/W000

Random SS range control

3-0SS_TRI_CTRLR/W0000

Triangle SS frequency and range control

7.6.1.33 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]

SS_CTRL2 is shown in Figure 7-48 and described in Table 7-40.

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Figure 7-48 SS_CTRL2 Register
76543210
TM_FREQ_CTRL
R/W
Table 7-40 SS_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-0TM_FREQ_CTRLR/W01010000

Control ramp frequency in manual mode, F=61440000/N

7.6.1.34 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in Figure 7-49 and described in Table 7-41.

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Figure 7-49 SS_CTRL3 Register
76543210
TM_DSTEP_CTRLTM_USTEP_CTRL
R/WR/W
Table 7-41 SS_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
7-4SS_TM_DSTEP_CTRLR/W0001

Control triangle mode spread spectrum fall step in ramp ss manual mode

3-0SS_TM_USTEP_CTRLR/W0001

Control triangle mode spread spectrum rise step in ramp ss manual mode

7.6.1.35 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in Figure 7-50 and described in Table 7-42.

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Figure 7-50 SS_CTRL4 Register
76543210
RESERVEDTM_AMP_CTRLSS_TM_PERIOD_BOUNDRY
R/WR/WR/W
Table 7-42 SS_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-5TM_AMP_CTRLR/W01

Control ramp amp ctrl in ramp ss manual model

4-0SS_TM_PERIOD_BOUNDRYR/W00100

Control triangle mode spread spectrum boundary in ramp ss manual mode

7.6.1.36 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in Figure 7-51 and described in Table 7-43.

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Figure 7-51 CHAN_FAULT Register
76543210
RESERVEDCH1_DC_1CH2_DC_1CH1_OC_ICH2_OC_I
RRRRR
Table 7-43 CHAN_FAULT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0000

This bit is reserved

3CH1_DC_1R0

Left channel DC fault

2CH2_DC_1R0

Right channel DC fault

1CH1_OC_IR0

Left channel over current fault

0CH2_OC_IR0

Right channel over current fault

7.6.1.37 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in Figure 7-52 and described in Table 7-44.

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Figure 7-52 GLOBAL_FAULT1 Register
76543210
OTP_CRC_ERRORBQ_WR_ERRORCLK_FAULT_IPVDD_OV_IPVDD_UV_I
RRRRR
Table 7-44 GLOBAL_FAULT1 Register Field Descriptions
BitFieldTypeResetDescription
7OTP_CRC_ERRORR0h

Indicate OTP CRC check error.

6BQ_WR_ERRORR0h

The recent BQ is written failed

5-3RESERVEDR0h

This bit is reserved

2CLK_FAULT_IR0h

Clock fault

1PVDD_OV_IR0h

PVDD OV fault

0PVDD_UV_IR0h

PVDD UV fault

7.6.1.38 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in Figure 7-53 and described in Table 7-45.

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Figure 7-53 GLOBAL_FAULT2 Register
76543210
RESERVEDRESERVEDOTSD_I
RRR
Table 7-45 GLOBAL_FAULT2 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0000000

This bit is reserved

0OTSD_IR0

Over temperature shut down fault

7.6.1.39 OT WARNING Register (Offset = 73h) [reset = 0x00]

OT_WARNING is shown in Figure 7-54 and described in Table 7-46.

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Figure 7-54 OT_WARNING Register
76543210
RESERVEDRESERVEDOTWRESERVED
RRRRRR
Table 7-46 OT_WARNING Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00

This bit is reserved

5-3RESERVEDR000

This bit is reserved

2OTWR0

Over temperature warning ,135C

1-0RESERVEDR00

This bit is reserved

7.6.1.40 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in Figure 7-55 and described in Table 7-47.

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Figure 7-55 PIN_CONTROL1 Register
76543210
MASK_OTSDMASK_DVDD_UVMASK_DVDD_OVMASK_CLK_FAULTMASK_PVDD_UVMASK_PVDD_OVMASK_DCMASK_OC
R/WR/WR/WR/WR/WR/WR/WR/W
Table 7-47 PIN_CONTROL1 Register Field Descriptions
BitFieldTypeResetDescription
7MASK_OTSDR/W0

Mask OTSD fault report

6MASK_DVDD_UVR/W0

Mask DVDD UV fault report

5MASK_DVDD_OVR/W0

Mask DVDD OV fault report

4MASK_CLK_FAULTR/W0

Mask clock fault report

3MASK_PVDD_UVR/W0

Mask PVDD UV fault report

2MASK_PVDD_OVR/W0

Mask PVDD OV fault report

1MASK_DCR/W0

Mask DC fault report

0MASK_OCR/W0

Mask OC fault report

7.6.1.41 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in Figure 7-56 and described in Table 7-48.

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Figure 7-56 PIN_CONTROL2 Register
76543210
RESERVEDCLKFLT_LATCH_ENOTSD_LATCH_ENOTW_LATCH_ENMASK_OTWRESERVED
R/WR/WR/WR/W
Table 7-48 PIN_CONTROL2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W11

This bit is reserved

5CLKFLT_LATCH_ENR/W1

Enable clock fault latch

4OTSD_LATCH_ENR/W1

Enable OTSD fault latch

3OTW_LATCH_ENR/W1

Enable OT warning latch

2MASK_OTWR/W0

Mask OT warning report

1-0RESERVEDR/W00

This bit is reserved

7.6.1.42 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in Figure 7-57 and described in Table 7-49.

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Figure 7-57 MISC_CONTROL Register
76543210
DET_STATUS_LATCHRESERVEDOTSD_AUTO_REC_ENRESERVED
R/WR/WR/WR/W
Table 7-49 MISC_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7DET_STATUS_LATCHR/W0

1:Latch clock detection status

0:Don't latch clock detection status

6-5RESERVEDR/W00

This bit is reserved

4OTSD_AUTO_REC_ENR/W0

OTSD auto recovery enable

3-0RESERVEDR/W0000

This bit is reserved

7.6.1.43 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in Figure 7-58 and described in Table 7-50.

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Figure 7-58 FAULT_CLEAR Register
76543210
ANALOG_FAULT_CLEARRESERVED
WR/W
Table 7-50 FAULT_CLEAR Register Field Descriptions
BitFieldTypeResetDescription
7ANALOG_FAULT_CLEARW0

WRITE CLEAR BIT.

Once write this bit to 1, device will clear analog fault

6-0RESERVEDR/W0000000

This bit is reserved