SLOS670B November   2010  – December 2016 TAS5727

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  DC Electrical Characteristics
    6. 8.6  AC Electrical Characteristics (BTL, PBTL)
    7. 8.7  PLL Input Parameters and External Filter Components
    8. 8.8  Serial Audio Ports Slave Mode
    9. 8.9  I2C Serial Control Port Operation
    10. 8.10 Reset Timing (RESET)
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Power Supply
      2. 10.3.2  I2C Address Selection and Fault Output
        1. 10.3.2.1 I2C Chip Select
        2. 10.3.2.2 I2C Device Address Change Procedure
        3. 10.3.2.3 Fault Indication
      3. 10.3.3  Device Protection Systems
        1. 10.3.3.1 Overcurrent (OC) Protection With Current Limiting
        2. 10.3.3.2 Overtemperature Protection
        3. 10.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      4. 10.3.4  Clock, Auto Detection, and PLL
      5. 10.3.5  PWM Section
      6. 10.3.6  SSTIMER Functionality
      7. 10.3.7  Single-Filter PBTL Mode
      8. 10.3.8  I2C Serial Control Interface
        1. 10.3.8.1 General I2C Operation
        2. 10.3.8.2 Single- and Multiple-Byte Transfers
        3. 10.3.8.3 Single-Byte Write
        4. 10.3.8.4 Multiple-Byte Write
        5. 10.3.8.5 Single-Byte Read
        6. 10.3.8.6 Multiple-Byte Read
      9. 10.3.9  Audio Serial Interface
      10. 10.3.10 Serial Interface Control and Timing
        1. 10.3.10.1 I2S Timing
        2. 10.3.10.2 Left-Justified
        3. 10.3.10.3 Right-Justified
      11. 10.3.11 Dynamic Range Control (DRC)
      12. 10.3.12 PWM Level Meter
    4. 10.4 Device Functional Modes
      1. 10.4.1 Stereo BTL Mode
      2. 10.4.2 Mono PBTL Mode
    5. 10.5 Programming
      1. 10.5.1 26-Bit 3.23 Number Format
    6. 10.6 Register Maps
      1. 10.6.1  Clock Control Register (0x00)
      2. 10.6.2  Device Id Register (0x01)
      3. 10.6.3  Error Status Register (0x02)
      4. 10.6.4  System Control Register 1 (0x03)
      5. 10.6.5  Serial Data Interface Register (0x04)
      6. 10.6.6  System Control Register 2 (0x05)
      7. 10.6.7  Soft Mute Register (0x06)
      8. 10.6.8  Volume Registers (0x07, 0x08, 0x09)
      9. 10.6.9  Volume Configuration Register (0x0E)
      10. 10.6.10 Modulation Limit Register (0x10)
      11. 10.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 10.6.12 PWM Shutdown Group Register (0x19)
      13. 10.6.13 Start/Stop Period Register (0x1A)
      14. 10.6.14 Oscillator Trim Register (0x1B)
      15. 10.6.15 BKND_ERR Register (0x1C)
      16. 10.6.16 Input Multiplexer Register (0x20)
      17. 10.6.17 Channel 4 Source Select Register (0x21)
      18. 10.6.18 PWM Output MUX Register (0x25)
      19. 10.6.19 DRC Control Register (0x46)
      20. 10.6.20 PWM Switching Rate Control Register (0x4F)
      21. 10.6.21 Bank Switch and EQ Control (0x50)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Stereo Stereo Bridge Tied Load Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Component Selection and Hardware Connections
          2. 11.2.1.2.2 I2C Pullup Resistors
          3. 11.2.1.2.3 Digital I/O Connectivity
          4. 11.2.1.2.4 Recommended Start-Up and Shutdown Procedures
            1. 11.2.1.2.4.1 Initialization Sequence
            2. 11.2.1.2.4.2 Normal Operation
            3. 11.2.1.2.4.3 Shutdown Sequence
            4. 11.2.1.2.4.4 Power-Down Sequence
        3. 11.2.1.3 Application Curves
      2. 11.2.2 Mono Parallel Bridge Tied Load Application
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 DVDD and AVDD Supplies
    2. 12.2 PVDD Power Supply
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Development Support
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

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11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

11.1 Application Information

The typical connection diagram highlights the required external components and system level connections for proper operation of the device in several popular system examples.

Each of these configurations can be realized using the Evaluation Module (EVM) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.

11.2 Typical Applications

11.2.1 Stereo Stereo Bridge Tied Load Application

TAS5727 Stereo_BTL_Mode.gif Figure 40. TAS5727 Stereo Application

11.2.1.1 Design Requirements

Table 27 lists the design parameters for this example.

Table 27. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 26 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low-Pass Filter(1)
Speaker 4-Ω minimum
(1) Refer to SLOA119 for a detailed description of the filter design.

11.2.1.2 Detailed Design Procedure

11.2.1.2.1 Component Selection and Hardware Connections

The typical connections required for proper operation of the device can be found on the TAS5727 User’s Guide (SLOU346). The device was tested this list of components, deviation from this typical application components unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. The application report Class-D LC Filter Design (SLOA119) offers a detailed description on proper component selection and design of the output filter based upon the modulation used, desired load, and response.

11.2.1.2.2 I2C Pullup Resistors

Customary pullup resistors are required on the SCL and SDA signal lines. These pullups are not shown in the typical application circuits, because they are shared by all of the devices on the I2C bus, and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I2C Specification.

11.2.1.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5727 are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count.

11.2.1.2.4 Recommended Start-Up and Shutdown Procedures

TAS5727 T0419-06_SLOS670.gif Figure 41. Recommended Command Sequence
TAS5727 T0420-05_LOS645.gif Figure 42. Power-Loss Sequence

11.2.1.2.4.1 Initialization Sequence

Use the following sequence to power up and initialize the device:

  1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
  2. Initialize digital inputs and PVDD supply as follows:
    • Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1, and wait at least another 13.5 ms.
    • Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
  3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
  4. Configure the DAP through I2C (see User's Guide for typical values).
  5. Configure remaining registers.
  6. Exit shutdown (sequence defined below).

11.2.1.2.4.2 Normal Operation

The following are the only events supported during normal operation:

  1. Writes to master/channel volume registers
  2. Writes to soft-mute register
  3. Enter and exit shutdown (sequence defined below)

NOTE

Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD power-up ramp (where tstart is specified by register 0x1A).

11.2.1.2.4.3 Shutdown Sequence

Enter:

  1. Write 0x40 to register 0x05.
  2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A).
  3. If desired, reconfigure by returning to step 4 of initialization sequence.

Exit:

  1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD power-up ramp).
  2. Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A).
  3. Proceed with normal operation.

11.2.1.2.4.4 Power-Down Sequence

Use the following sequence to power down the device and its supplies:

  1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms.
  2. Assert RESET = 0.
  3. Drive digital inputs low and ramp down PVDD supply as follows:
    • Drive all digital inputs low after RESET has been low for at least 2 µs.
    • Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at least 2 µs.
  4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2.5 V below the digital inputs.

11.2.1.3 Application Curves

TAS5727 Graph3_THDvFreq24V8R.png Figure 43. Total Harmonic Distortion + Noise vs Frequency
TAS5727 Graph10_EffvPo12V18V24V8R.png

NOTE:

Dashed lines represent thermally limited region.
Figure 44. Efficiency vs Total Output Power

11.2.2 Mono Parallel Bridge Tied Load Application

TAS5727 B0264-26_SLOS838.gif Figure 45. TAS5727 Mono Application

11.2.2.1 Design Requirements

Table 28 lists the design parameters for this example.

Table 28. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 26 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low-Pass Filter(1)
Speaker 2-Ω minimum
(1) Refer to SLOA119 for a detailed description of the filter design.

11.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

11.2.2.3 Application Curves

Refer to Application Curves.