ZHCS930A May   2012  – March 2015 TAS5614LA

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Specification Stereo (BTL)
    7. 6.7 Audio Specification 4 Channels (SE)
    8. 6.8 Audio Specification Mono (PBTL)
    9. 6.9 Typical Characteristics
      1. 6.9.1 BTL Configuration
      2. 6.9.2 SE Configuration
      3. 6.9.3 PBTL Configuration
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Power Supplies
        1. 7.3.1.1 Boot Strap Supply
      2. 7.3.2  System Power-Up and Power-Down Sequence
        1. 7.3.2.1 Powering Up
        2. 7.3.2.2 Powering Down
      3. 7.3.3  Start-up and Shutdown Ramp Sequence
      4. 7.3.4  Unused Output Channels
      5. 7.3.5  Device Protection System
      6. 7.3.6  Pin-to-Pin Short-Circuit Protection (PPSC)
      7. 7.3.7  Overtemperature Protection
      8. 7.3.8  Overtemperature Warning, OTW
      9. 7.3.9  Undervoltage Protection (UVP) and Power-On Reset (POR)
      10. 7.3.10 Error Reporting
      11. 7.3.11 Fault Handling
      12. 7.3.12 Device Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Selection Pins
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 System Design Consideration
    2. 8.2 Typical Applications
      1. 8.2.1 Typical BTL Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical SE Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Typical PBTL Configuration
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
      2. 10.1.2 PVDD Capacitor Recommendation
      3. 10.1.3 Decoupling Capacitor Recommendation
      4. 10.1.4 Circuit Component and Printed Circuit Board Recommendation
        1. 10.1.4.1 Circuit Component Requirements
        2. 10.1.4.2 Printed Circuit Board Requirements
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DDV Package
44-Pin HTSSOP
Top View
TAS5614LA po2_DDV_las813.gif

Pin Functions

PIN I/O/P(1) DESCRIPTION
NAME NO.
AVDD 13 P Internal voltage regulator, analog section
BST_A 44 P Bootstrap pin, A-side
BST_B 43 P Bootstrap pin, B-side
BST_C 24 P Bootstrap pin, C-side
BST_D 23 P Bootstrap pin, D-side
CLIP 18 O Clipping warning, open drain, active low
C_START 7 O Start-up ramp
DVDD 8 P Internal voltage regulator, digital section
FAULT 16 O Shutdown signal, open drain, active low
GND 9, 10, 11, 12, 25,
26, 33, 34, 41, 42		 P Ground
GVDD_AB 1 P Gate-drive voltage supply, AB-side
GVDD_CD 22 P Gate-drive voltage supply, CD-side
INPUT_A 5 I PWM input signal for half-bridge A
INPUT_B 6 I PWM input signal for half-bridge B
INPUT_C 14 I PWM input signal for half-bridge C
INPUT_D 15 I PWM input signal for half-bridge D
M1 19 I Mode selection 1 (LSB)
M2 20 I Mode selection 2
M3 21 I Mode selection 3 (MSB)
OC_ADJ 3 O Overcurrent threshold programming pin
OTW 17 O Overtemperature warning, open drain, active low
OUT_A 39, 40 O Output, half-bridge A
OUT_B 35 O Output, half-bridge B
OUT_C 32 O Output, half-bridge C
OUT_D 27, 28 O Output, half-bridge D
PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B
PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D
RESET 4 I Device reset input, active low
VDD 2 P Input power supply
PowerPAD™ – P Ground, connect to grounded heat sink
(1) I = Input, O = Output, P = Power