12.1 Layout Guidelines

1. Use 45 degree bends (chamfered corners), instead of right-angle (90°) bends. Right-angle bends increase the effective trace width, which changes the differential trace impedance creating large discontinuities. A 45 degree bend is seen as a smaller discontinuity.
2. Place passive components within the signal path, such as source-matching resistors or ac-coupling capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b), the resulting discontinuity, however, is limited to a far narrower area
3. When routing traces next to a via or between an array of vias, make sure that the via clearance section does not interrupt the path of the return current on the ground plane below.
4. Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the board during TDR testing.
5. Use solid power and ground planes for 100 Ω impedance control and minimum power noise. For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane.
6. For 100 Ω differential impedance, use the smallest trace spacing possible, which is usually specified by the PCB vendor.
7. Keep the trace length as short as possible to minimize attenuation.
8. Place bulk capacitors (that is, 10 μF) close to power sources, such as voltage regulators or where the power is supplied to the PCB.

12.2 Layout Example

Figure 19. Layout Example