SLLS259J November   1996  – October 2016 SN75LVDS82

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics 
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 LVDS Input Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low Power Mode
      2. 9.4.2 Test Patterns
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Signal Connectivity
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power Up Sequence
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section describes provides information on how each signal should be connected from the graphic source through the SN75LVDS83B and the SN75LVDS82 to the LCD panel input.

10.2 Typical Applications

10.2.1 Signal Connectivity

SN75LVDS82 ai_24bit_lls259.gif
A. The five 100-Ω terminating resistors are recommended to be 0603 types.
B. NA — not applicable, these unused inputs should be left open.
Figure 16. 24-Bit Color Host to 24-Bit LCD Flat Panel Display Application

10.2.1.1 Design Requirements

For this design example, use the parameters shown in Table 2.

Table 2. Design Parameters

DESIGN PARAMETERS VALUE
VDD Main Power Supply 3.3 V
Input LVDS Clock Frequency 31 - 68 MHz
RL Differential Input Termination Resistance 100 Ω
LVDS Input Lanes 4
Color depth 24 Bit

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Power Up Sequence

The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended.

Power up sequence (SN75LVDS82 /SHTDN input initially low):

  1. Ramp up LCD power (maybe 0.5 ms to 10 ms) but keep backlight turned off.
  2. Wait for additional 0-200 ms to ensure display noise will not occur.
  3. Enable video source output; start sending black video data.
  4. Toggle SN75LVDS82 shutdown to SHTDN = VIH.
  5. Send > 1 ms of black video data; this allows the SN75LVDS82 to be phase locked, and the display to show black data first.
  6. Start sending true image data.
  7. Enable backlight.

Power Down sequence (SN75LVDS82 SHTDN input initially high):

  1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low
  2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for > 2 frame times.
  3. Set SN75LVDS82 input SHTDN = GND; wait for 250 ns.
  4. Disable the video output of the video source.
  5. Remove power from the LCD panel for lowest system power.

10.2.1.3 Application Curves

SN75LVDS82 LVDS_Clock.gif Figure 17. LVDS Clock
SN75LVDS82 Output_Clock.gif Figure 18. Output Clock