SCAS297O January   1993  – June 2026 SN74LVC540A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   5
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics, SN74LVC540A
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
    1. 6.1 17
  9.   18
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DGV|20
  • DB|20
  • NS|20
  • DW|20
  • PW|20
  • DGS|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Description

The SN74LVC540A contains eight inverters with 3-state outputs. The 540 function has the same functionality as the 240 function and has a flow-through pinout. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74LVC540A PW (TSSOP, 20) 6.5mm × 6.4mm 6.5mm × 4.4mm
DW (SOIC, 20) 12.80mm × 10.3mm 12.8mm × 7.5mm
DB (SSOP, 20) 7.2mm × 7.8mm 7.50mm × 5.3mm
NS (SOP, 20) 12.6mm × 7.8mm 12.6mm × 5.3mm
DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3.0mm
RKS (VQFN, 20) 4.5mm × 2.5mm 4.5mm × 2.5mm
DGV (TVSOP, 20) 5.0mm × 6.4mm 5.0mm × 4.4mm
(1) For more information, see Mechanical, Packaging, and Orderable Information.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74LVC540A Functional Block Diagram Functional Block Diagram