SCES195N April   1999  – August 2015 SN74LVC2G04

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DBV|6
  • DRL|6
  • YZP|6
  • DCK|6
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC2G04 contains two logic inverters. It can be used in a wide variety of applications, with this being one example. Because this part has overvoltage tolerant inputs, it can be used for down translating logic levels. This example explains the method used for down-translating with this logic gate.

9.2 Typical Application

SN74LVC2G04 sces195_app2.gifFigure 3. Application Schematic

9.2.1 Design Requirements

The inputs, X and Y in Figure 3, to this device can be any value from –0.5 V to 6.5 V, according to Absolute Maximum Ratings. Because the input limits are not associated with VCC, down-translation is simple. The output voltage is selected with VCC, and so long as the input logic voltage is larger than VIH, found in Recommended Operating Conditions, the output will trigger properly.

9.2.2 Detailed Design Procedure

  1. Recommended Input Conditions
  2. Recommend Output Conditions
    • Load currents should not exceed (IO max) per output and should not exceed total current (continuous current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings table.
    • Outputs should not be pulled above VCC.

9.2.3 Application Curve

There is a slight delay from input to output in addition to the voltage change. Figure 4 shows the expected output of the SN74LVC2G04 when an input is switched from 0 to 5 V and VCC is set at 1.8 V. With VCC set to 1.8 V, the output switches at 1.17 V (0.65 × VCC), and therefore the input can be anything from 1.18 V up to 6.5 V and the SN74LVC2G04 will work perfectly.

SN74LVC2G04 app2_plot.pngFigure 4. Simulated Voltage Down-Translation from 5-V Input to 1.8-V Output With tpd = 3.4 ns.