ZHCSRA6N April   1998  – December 2023 SN74LV373A

PRODMIX  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 5.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 5.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 5.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 5.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 5.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 5.12 Noise Characteristics
    13. 5.13 Operating Characteristics
    14. 5.14 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 22
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3.     Power Supply Recommendations
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Community Resources
    3. 9.3 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DGV|20
  • DB|20
  • NS|20
  • PW|20
  • DW|20
  • RGY|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1 Overview

The SN74LV373A device is an octal transparent D-type latch designed for 2 V to 5.5 V VCC operation.

When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

At power-up, the state of the Q outputs are not predictable until the first valid clock.

A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.