ZHCSW01J June   1998  – April 2024 SN74AHCT594

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Noise Characteristics
    9. 5.9  Operating Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Links
    2. 9.2 Trademarks
    3. 9.3 静电放电警告
    4. 9.4 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PW|16
  • DB|16
  • NS|16
  • N|16
  • D|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.6 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
PARAMETERTA = 25°C–40°C to 85°C–40°C to 125°CUNIT
MINMAXMINMAXMINMAX
twPulse durationRCLK or SRCLK high or low55.56.5ns
RCLR or SRCLR low5.25.56
tsuSetup timeSER before SRCLK↑333.5ns
SRCLK↑ before RCLK↑(1)555.5
SRCLR low before RCLK↑555.5
SRCLR high (inactive) before SRCLK↑2.93.34
RCLR high (inactive) before RCLK↑3.43.84.5
thHold timeSER after SRCLK↑222.5ns
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.