6 Parameter Measurement Information

Figure 6-1 Receiver Voltage and Current Definitions

Table 6-1 Type-1 Receiver Input Threshold Test Voltages

APPLIED VOLTAGES		RESULTING DIFFERENTIAL INPUT VOLTAGE	RESULTING COMMON-MODE INPUT VOLTAGE	RECEIVER OUTPUT⁽¹⁾
V_IA	V_IB	V_ID	V_IC	RECEIVER OUTPUT⁽¹⁾
2.400	0.000	2.400	1.200	H
0.000	2.400	–2.400	1.200	L
3.400	3.365	0.035	3.3825	H
3.365	3.400	–0.035	3.3825	L
–0.965	–1	0.035	–0.9825	H
–1	–0.965	–0.035	–0.9825	L

(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)

Table 6-2 Type-2 Receiver Input Threshold Test Voltages

APPLIED VOLTAGES		RESULTING DIFFERENTIAL INPUT VOLTAGE	RESULTING COMMON-MODE INPUT VOLTAGE	RECEIVER OUTPUT⁽¹⁾
V_IA	V_IB	V_ID	V_IC	RECEIVER OUTPUT⁽¹⁾
2.400	0.000	2.400	1.200	H
0.000	2.400	–2.400	1.200	L
3.400	3.265	0.135	3.3325	H
3.4000	3.335	0.05065	3.3675	L
–0.865	–1	0.135	–0.9325	H
-0.935	–1	0.065	–0.9675	L

(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)

A. All input pulses are supplied by a generator having the following characteristics: t_r or t_f ≤ 1ns, Frequency = 1MHz, duty cycle = 50 ± 5%. C_L is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.

B. The measurement is made on test equipment with a –3dB bandwidth of at least 1GHz.

Figure 6-2 Receiver Timing Test Circuit and Waveforms

A. All input pulses are supplied by a generator having the following characteristics: t_r or t_f ≤ 1ns, frequency = 1MHz, duty cycle = 50 ± 5%.

B. R_L is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T

C. C_L is the instrumentation and fixture capacitance within 2 cm of the D.U.T. and ±20%. The measurement is made on test equipment with a –3dB bandwidth of at least 1GHz.

Figure 6-3 Receiver Enable/Disable Time Test Circuit and Waveforms

A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.

B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software.

C. All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer.

D. Period jitter and cycle-to-cycle jitter are measured using a 125MHz 50 ± 1% duty cycle clock input. Measured over 75K samples.

E. Deterministic jitter and random jitter are measured using a 250Mbps 2¹⁵^-1 PRBS input. Measured over BER = 10^-12

Figure 6-4 Receiver Jitter Measurement Waveforms