SLLS881G December   2007  – October 2014 SN65LVDS315

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Device Electrical Characteristics
    6. 6.6 Output Electrical Characteristics
    7. 6.7 Input Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Blanking Power Consumption Test Pattern
    2. 7.2 Maximum Power Consumption Test Pattern
    3. 7.3 Jitter Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Frame Counter Size
      2. 8.3.2 Data Formats
      3. 8.3.3 Parallel Input Port Timing Information
      4. 8.3.4 MIPI CSI-1 / CCP2-Class 0 Interface
      5. 8.3.5 Frame Structure and Synchronization Codes
      6. 8.3.6 Preventing Wrong Synchronization
      7. 8.3.7 Frame Structure
      8. 8.3.8 VS and HS Timing to Generate the Correct Control Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Powerdown Modes
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Standby Mode
      2. 8.4.2 Active Modes
        1. 8.4.2.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.2.2 Transmit Mode
      3. 8.4.3 Status Detect and Operating Modes Flow Diagram
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Receiver Termination Requirement
      2. 9.1.2 Preventing Control Inputs From Increased Leakage Currents
    2. 9.2 Typical Application
      1. 9.2.1 VGA Camera Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Calculation Example: VGA Camera Sensor
          2. 9.2.1.2.2 Typical Application Frequencies
            1. 9.2.1.2.2.1 8-Bit Camera Application
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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4 Revision History

Changes from F Revision (September 2012) to G Revision

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Replaced Dissipation Ratings with Thermal Information Go

Changes from E Revision (August 2012) to F Revision

  • deleted ΔVOCM(SS) and VOCM(PP) From the OUTPUT ELECTRICAL CHARACTERISTICSGo
  • Changed the RECEIVER TERMINATION REQUIREMENT sectionGo

Changes from D Revision (February 2012) to E Revision

  • Added the RECEIVER TERMINATION REQUIREMENT sectionGo

Changes from C Revision (June 2001) to D Revision

  • Changed Feature From: Pixel Clock Range 3.5–26 MHz To: Pixel Clock Range 3.5–27 MHzGo
  • Chnaged the pin function for FSEL From: FSEL=1: DCLK input frequencies from 7.0 MHz to 26 MHz are supported To: FSEL=1: DCLK input frequencies from 7.0 MHz to 27 MHz are supportedGo
  • Changed Data clock frequency for FSEL = 1 in the ROC table From: MAX = 26 MHz To: MAX = 27 MHz Go
  • Changed the ROC table section MODE, TXEN, FSEL To: MODE, TXENGo
  • Added section FSEL to the ROC tableGo
  • Changed the TYPICAL APPLICATION FREQUENCIES section. From: The SN65LVDS315 in display mode supports pixel clock frequencies from 7 MHz to 26 MHz To: The SN65LVDS315 in display mode supports pixel clock frequencies from 7 MHz to 27 MHzGo

Changes from B Revision (November 2008) to C Revision

  • Changed Figure 17: Note E - From: "Time between HS falling and HS rising edge" To: "Time between VS falling and VS rising edgeGo
  • Changed the Acquire Mode (PLL Approaches Lock) section. From: "HS low-to-high" To: VS low-to-high and From "MODE is set low"; To: "MODE is set high" Go
  • Changed text in the VGA CAMERA APPLICATION section From: The pixel clock rate is 11 MHz, assuming ≉10% blanking overhead. To: The pixel clock rate is 11 MHz, assuming ≈20% blanking overheadGo

Changes from A Revision (March 2008) to B Revision

  • Changed the Absoulute Maximum Ratings table - Voltage range at any input terminal value From: –0.5 to 2.175 To: –0.5 to VDDIO + 0.5VGo

Changes from * Revision (December 2007) to A Revision

  • Changed the document from: Product Preview To: ProductionGo