SLLS575A AUGUST   2003  – July 2015 SN65LVDS049

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Device Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Dissipation Rating
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Driver Offset
      2. 8.3.2 Receiver Open Circuit Fail-Safe
      3. 8.3.3 Receiver Common-Mode Range
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Point-to-Point Communications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Bypass Capacitance
          2. 9.2.1.2.2  Driver Supply Voltage
          3. 9.2.1.2.3  Driver Input Voltage
          4. 9.2.1.2.4  Driver Output Voltage
          5. 9.2.1.2.5  Interconnecting Media
          6. 9.2.1.2.6  PCB Transmission Lines
          7. 9.2.1.2.7  Termination Resistor
          8. 9.2.1.2.8  Receiver Supply Voltage
          9. 9.2.1.2.9  Receiver Input Common-Mode Range
          10. 9.2.1.2.10 Receiver Input Signal
          11. 9.2.1.2.11 Receiver Output Signal
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Multidrop Communications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Interconnecting Media
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage(2), VCC –0.3 4 V
Voltage DIN, ROUT, EN, or EN –0.3 (VCC + 0.3 V) V
RIN+ or RIN- –0.3 4
DOUT+ or DOUT- –0.3 3.9
LVDS output short circuit duration (DOUT+, DOUT-) Continuous
Continuous power dissipation See Dissipation Rating
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 °C
Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) RIN+, RIN–, DOUT+, and DOUT– ±10000 V
All pins ±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
Receiver input voltage GND V
Common-mode input voltage, VIC
SN65LVDS049 Q_VID_lls575.gif
SN65LVDS049 Q_24VID_lls575.gif
 V
VCC - 0.8 V
Operating free-air temperature, TA –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) SN65LVDS049 UNIT
PW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 10.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.8 °C/W
RθJB Junction-to-board thermal resistance 45.4 °C/W
ψJT Junction-to-top characterization parameter 2.6 °C/W
ψJB Junction-to-board characterization parameter 44.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Device Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
INPUT DC SPECIFICATIONS (DIN, EN, EN)
VIH Input high voltage 2 VCC V
VIL Input low voltage GND 0.8 V
IIH Input high current VIN = VCC –10 3 10 µA
IIL Input low current VIN = GND –10 1 10 µA
VCL Input clamp voltage ICL = -18 mA –1.5 –0.8 V
LVDS OUTPUT DC SPECIFICATIONS (DOUT+, DOUT–)
|VOD| Differential output voltage RL = 100 Ω, See Figure 1 250 350 450 V
Δ|VOD| Change in magnitude of VOD for
complementary output states		 –35 1 35 mV
VOS Offset voltage 1.125 1.2 1.375 V
ΔVOS Change in magnitude of VOS for
complementary output states		 –25 1 25 mV
IOS Output short-circuit current Enabled
DIN = VCC and DOUT+ = 0 V, or
DIN = GND and DOUT- = 0 V 		-4.5 -9 mA
IOSD Differential output short-circuit current(2) Enabled, VOD = 0 V –3.6 -9 mA
IOFF Power-off leakage VCC = 0 V or Open;
VO = 0 or 3.6 V 		–20 0 20 µA
IOZ Output high-impedance current EN = 0 V and EN = VCC,
VO = 0 or VCC		 –10 0 10 µA
LVDS INPUT DC SPECIFICATIONS (RIN+, RIN–)
VIT+ Differential input high threshold VCM = 1.2 V, 0.05 V, 2.35 V 100 mV
VIT- Differential input low threshold VCM = 1.2 V, 0.05 V, 2.35 V –100 mV
VCMR Common-mode voltage range VID = ± 100 mV 0.05 2.35 V
IIN Input current VCC = 3.6 V, VIN = 0 V or 2.8 V –20 20 µA
VCC= 0 V, VIN = 0 V, 2.8 V, or 3.6 V –20 20
OUTPUTS DC SPECIFICATIONS (ROUT)
VOH Output high voltage IOH = –0.4 mA, VID = 200 mV 2.7 3.3 V
VOL Output low voltage IOL = 2 mA, VID = –200 mV 0.05 0.25 V
IOZ Output high-impedance current Disabled, VOUT = 0 V or VCC –10 0 10 µA
DEVICE DC SPECIFICATIONS
ICC Power supply current
(LVDS loaded, enabled)		 EN = 3.3 V, DIN = VCC or Gnd, 100-Ω differential LVDS loads 17 35 mA
ICCZ High-impedance supply current (disabled) No loads, EN = 0 V 1 25 mA
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) Output short-circuit current (IOS) is specified as magnitude only; the minus sign indicates direction only

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
LVDS OUTPUTS (DOUT+, DOUT-)
tPLHD Differential propagation delay low to high RL = 100 Ω,
CL = 15 pF distributed,
See Figure 2		 1.3 2 ns
tPHLD Differential propagation delay high to low 1.4 2 ns
tsk(p) Differential pulse skew (|tPHL - tPLH|) 0 0.15 0.4 ns
tsk(o) Differential channel-to-channel skew(2) 0 0.05 0.5 ns
tsk(pp) Differential part-to-part skew(3) 0 1 ns
tr Differential rise time 0.2 0.5 1 ns
tf Differential fall time 0.2 0.5 1 ns
tPHZ Disable time, high level to high impedance RL = 100 Ω,
CL = 15 pF distributed,
See Figure 3		 2.7 4 ns
tPLZ Disable time, low level to high impedance 2.7 4 ns
tPZH Enable time, high impedance to high level 1 5 8 ns
tPZL Enable time, high impedance to low level 1 5 8 ns
fMAX Maximum operating frequency(4) 250 MHz
LVCMOS OUTPUTS (ROUT)
tPLH Propagation delay low to high VID= 200 mV,
CL = 15 pF distributed,
See Figure 4		 0.5 1.9 3.5 ns
tPHL Propagation delay high to low 0.5 1.7 3.5 ns
tsk(p) Pulse skew (|tPHL - tPLH|) 0 0.2 0.4 ns
tsk(o) Channel-to-channel skew(5) 0 0.05 0.5 ns
tsk(pp) Part-to-part skew(6) 0 1 ns
tr Rise time 0.3 0.5 1.4 ns
tf Fall time 0.3 0.5 1.4 ns
tPHZ Disable time, high level to high impedance CL = 15 pF distributed,
See Figure 5		 3 7.2 9 ns
tPLZ Disable time, low level to high impedance 2.5 4 8 ns
tPZH Enable time, high impedance to high level 2.5 4.2 7 ns
tPZL Enable time, high impedance to low level 2 3.3 7 ns
fMAX Maximum operating frequency(7) 200 250 MHz
(1) All typical values are at 25°C and with a 3.3 V supply.
(2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
(5) tsk(lim) is the maximum delay time difference between drivers over temperature, VCC, and process.
(6) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate wf(MAX) generaith the same supply voltages, at the same temperature, and have identical packages and test circuits
(7) f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V. Output criteria: duty cycle = 45% to 55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching.

6.7 Dissipation Rating

PACKAGE CIRCUIT BOARD MODEL TA≤25°C
POWER RATING		 DERATING FACTOR(1)
ABOVE TA = 25°C 		TA = 85°C
POWER RATING
PW Low-K(2) 774 mW 6.2 mW/°C 402 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.

6.8 Typical Characteristics

SN65LVDS049 vod_load_lls575.gif
VCC = 3.3 V TA = 25°C
VOD vs. Load Resistance
SN65LVDS049 ps_cur_lls575.gif
VCC = 3.3 V TA = 25°C VID = 40 MVp-p
VI = 3 V RL = 100 Ω CL = 15-pF Distributed
Power Supply Current vs. Frequency