ZHCS378C September   2011  – March 2015 SN65HVD62

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 方框图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driver Amplitude Adjust
      2. 10.1.2 Direction Control
      3. 10.1.3 Direction Control Time Constant
      4. 10.1.4 Conversion Between dBm and Peak-to-peak Voltage
  11. 11器件和文档支持
    1. 11.1 文档支持
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

VALUES UNIT
MIN MAX
Supply voltage, VCC and VL –0.5 6 V
Voltage range at coax pins –0.5 6 V
Voltage range at logic pins –0.3 VL + 0.3 V
Logic Output Current –20 20 mA
TXOUT output current Internally limited
SYNCOUT output current Internally limited
Junction Temperature, TJ 170 °C
Storage temperature, TSTG –65 150
Continuous total power dissipation See the Thermal Information °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Thermal Information

THERMAL METRIC(1) SN65HVD62 UNIT
RGT (VQFN)
(16) PINS
RθJA Junction-to-ambient thermal resistance 49.4 °C/W
RθJCtop Junction-to-case (top) thermal resistance 64.2
RθJB Junction-to-board thermal resistance 22.9
ψJT Junction-to-top characterization parameter 1.7
ψJB Junction-to-board characterization parameter 22.9
RθJCbot Junction-to-case (bottom) thermal resistance 25.0
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Analog supply voltage 3 5.5 V
VL Logic supply voltage 1.6 5.5 V
VI(pp) Input signal amplitude at RXIN 1.12 Vpp
VIH High-level input voltage TXIN, DIRSET1, DIRSET2 70%VL VL V
XTAL1, XTAL2 70%VCC VCC
VIL Low-level input voltage TXIN, DIRSET1, DIRSET2 0 30%VL V
XTAL1, XTAL2 0 30%VCC
1/tUI Data signaling rate 9.6 115 kbps
FOSC Oscillator frequency HVD62 –30 ppm 8.704 30 ppm MHz
TA Operating free-air temperature –40 105 °C
TJ Junction Temperature –40 125 °C
RLOAD Load impedance between TXOUT to RXIN 50 Ω
Load impedance between RXIN and GND at fC (channel) 50
R1 Bias resistor between BIAS and RES 4.1 kΩ
R2 Bias resistor between RES and GND 10 kΩ
RSYNC Pull-up resistor between SYNCOUT and VCC 1 kΩ
VRES Voltage at RES pin 0.7 1.5 V
CC Coupling capacitance between RXIN and Coax (channel) 220 nF
CBIAS Capacitance between BIAS and GND 1 µF

7.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
100 ICC Supply current (VCC) TXIN = L (Active) DIRSET1 = L
DIRSET2 = H		 28 33 mA
101 TXIN = H (Quiescent) 25 31
102 TXIN = 115 kbps,
50% duty cycle		 27 33
99 (Standby) DIRSET1 = DIRSET2=H 12 17
103 IL Logic supply current TXIN = H, RXIN = DC input 50 µA
104 ΔVRXIN/
ΔVCC		 Receiver power supply rejection ratio VTXIN = VL 45 60 dB
LOGIC PINS
112 VOH High-level logic output voltage
(RXOUT, DIR)		 IOH = –4 mA for VL > 2.4V,
IOH = –2 mA for VL < 2.4V		 90%VL V
113 VOL Low-level logic output voltage
(RXOUT, DIR)		 IOL = 4 mA for VL > 2.4V,
IOL = 2 mA for VL < 2.4V		 10%VL V
114 IIH/IIL Logic input current (DIRSET1/2) -1 10 µA
IIH/IIL Logic input current (TXIN) -2 1 µA
COAX DRIVER
130 VOPP Peak-to-peak output voltage at device pin TXOUT (See Figure 19) VRES = 1.5 V (Maximum setting) 2.24 2.5 VPP
132 VRES = 0.7 V (Minimum setting) 1.17 1.3
130A VOPP Peak-to-peak voltage at coax out (See Figure 19) VRES = 1.5 V 5 6 dBm
132A VRES = 0.7 V -0.6 0.3
134 VOZ Off-state output voltage At TXOUT 1 mVpp
134A At coax out -60 dBm
136 Output emissions Coupled to coaxial cable with characteristic impedance 50 Ohms, as shown in Figure 1. With a recommended 470 pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by setup. Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see Figure 21
41 fo Output frequency (HVD62) 2.176 MHz
142 ∆f Output frequency variation –100 100 ppm
143 Zo Output impedance At 100 kHz 0.03 Ω
144 At 10 MHz 3.5 Ω
145 | IOS | Short-circuit output current TXOUT is also protected by a thermal shutdown circuit during short-circuit faults 300 450 mA
COAX RECEIVER
152 VIT Input threshold fIN = 2.176 MHz 79 112 158 mVPP
152A –18 –15 –12 dBm
154 ZIN Input impedance f = fO 11 21 kΩ
RECEIVER FILTER
160 fPB Passband VRXIN = 1.12VP_P 1.1 4.17 MHz
161 fREJ Receiver rejection range 2.176MHz carrier amplitude of 112.4 mVPP, Frequency band of spurious components with 800 mVPP allowed. 1.1 4.17 MHz
162 tnoise filter Receiver noise filter time (slow bit rate) DIRSET for 9.6kbps 4 µs
163 Receiver noise filter time (fast bit rate) DIRSET for > 9.6 kbps 2
XTAL AND SYNC
171 II Input leakage current XTAL1, XTAL2, 0V < VIN < VCC –15 15 µA
172 VOL Output low voltage SYNCOUT, with 1 kΩ resistor from SYNCOUT to VCC 0.4 V

7.6 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
201 tpAQ, tpQA Coax driver propagation delay See Figure 19 5 µs
202 tr, tf Coax receiver output rise/fall time CL = 15 pF, RL = 1 kΩ, See Figure 19 20 ns
203 tPHL, tPLH Receiver propagation delay See Figure 20 5.5 11 µs
204 Duty Cycle Coax receiver output duty cycle VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle 40% 60%
214 VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle 40% 60%
206 tDIR Direction control active duration DIRSET2 = DIRSET1 = GND or OPEN 1667 µs
207 DIRSET2 = GND, DIRSET1 = VL 417
208 DIRSET2 = VL, DIRSET1 = VL 137
209 tDIR Skew Direction control skew
(DIR to RXOUT)		 270 ns
210 tDIS Standby disable delay 300 mVPP at 2.176 MHz on RXIN 2 ms
211 tEN Standby enable delay 2

7.7 Typical Characteristics

SN65HVD62 C001_ook_9p6kbps.pngFigure 1. Low Frequency Emissions Spectrum with 9.6 kbps Signaling Rate
SN65HVD62 C003_38p4kbps.pngFigure 3. Low Frequency Emissions Spectrum with 38.4 kbps Signaling Rate
SN65HVD62 C005_115p2kbps.pngFigure 5. Low Frequency Emissions Spectrum with 115.2 kbps Signaling Rate
SN65HVD62 C007_zo_freq.pngFigure 7. Transmitter Output Impedance
SN65HVD62 C009_Icc_Vcc.pngFigure 9. Supply Current versus Supply Voltage while Transmitting
SN65HVD62 C011_Icc_temp.pngFigure 11. Supply Current versus Temperature in Standby Mode
SN65HVD62 C014_TXout_Temp.pngFigure 13. Transmitter Output Power versus Temperature
SN65HVD62 C015_Threshold_Temp.pngFigure 15. Receiver Input Threshold versus Temperature
SN65HVD62 C019_DC_ON_9p2.pngFigure 17. Receiver Duty Cycle with 9.6 kbps Signaling Rate
SN65HVD62 C002_OOK_High_9p6.pngFigure 2. High Frequency Emissions Spectrum with 9.6 kbps Signaling Rate
SN65HVD62 C004_OOK_high_38p4.pngFigure 4. High Frequency Emissions Spectrum with 38.4 kbps Signaling Rate
SN65HVD62 C006_OOK_High_115.pngFigure 6. High Frequency Emissions Spectrum with 115.2 kbps Signaling Rate
SN65HVD62 C008_Txout_vres.pngFigure 8. Transmit Power Adjustment
SN65HVD62 C010_Icc_Vcc_standby.pngFigure 10. Supply Current versus Supply Voltage in Standby Mode
SN65HVD62 C013_Txout_Vcc.pngFigure 12. Transmitter Output Power versus Supply Voltage
SN65HVD62 C014_Zin_Freq.pngFigure 14. Receiver Input Impedance versus Frequency
SN65HVD62 C017_Skew_Temp.pngFigure 16. DIR Output Delay versus Temperature
SN65HVD62 C021_DC_ON_115p2.pngFigure 18. Receiver Duty Cycle with 115.2 kbps Signaling Rate