ZHCSAT8G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
DSI
tGSDSI LP glitch suppression pulse width300ps
tSKSkew time from DSI Channel A to Channel B in dual DSI operationSee Figure 7-12
LVDS
tcOutput clock period6.4940ns
twHigh-level output clock (CLK) pulse duration4/7 tcns
t0Delay time, CLK↑ to 1st serial bit positiontc = 6.49 ns;
Input clock jitter < 25 ps
(REFCLK)
–0.150.15ns
t1Delay time, CLK↑ to 2nd serial bit position1/7 tc – 0.151/7 tc + 0.15ns
t2Delay time, CLK↑ to 3rd serial bit position2/7 tc – 0.152/7 tc + 0.15ns
t3Delay time, CLK↑ to 4th serial bit position3/7 tc – 0.153/7 tc + 0.15ns
t4Delay time, CLK↑ to 5th serial bit position4/7 tc – 0.154/7 tc + 0.15ns
t5Delay time, CLK↑ to 6th serial bit position5/7 tc – 0.155/7 tc + 0.15ns
t6Delay time, CLK↑ to 7th serial bit position6/7 tc – 0.156/7 tc + 0.15ns
trDifferential output rise-timesee Figure 7-1180500ps
tfDifferential output fall-time
LVDS CLK A to CLK B skew–1010ps
EN, ULPS, RESET
tenEnable time from EN or ULPStc(o) = 12.9 ns1ms
tdisDisable time to standby tc(o) = 12.9 ns0.1ms
tresetReset Time10ms
REFCLK
FREFCLKREFCLK Freqeuncy. Supported frequencies:
25 MHz - 15 4MHz
25154MHz
tr, tfREFCLK rise and fall time100ps1nss
tpjREFCLK Peak-to-Peak Phase Jitter50ps
DutyREFCLK Duty Cycle40%50%60%
REFCLK or DSI CLK (DACP/N, DBCP/N)
SSC_CLKINSSC enabled Input CLK center spread depth(2)0.5%1%2%
Modulation Frequency Range3060kHz
All typical values are at VCC = 1.8 V and TA = 25°C
For EMI reduction purpose, SN65DSI85 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N.
GUID-569CAA82-2F19-42DC-9938-3D56AC8DE75F-low.gifFigure 6-1 DSI Receiver Voltage Definitions
GUID-B18482EC-4C0C-4A51-B3DA-BD2E456A7021-low.gifFigure 6-2 Test Load and Voltage Definitions for FlatLink™ Outputs