ZHCSAT8G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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7.3.3 LVDS Pattern Generation

The SN65DSI85 supports a pattern generation feature on LVDS Channels. This feature can be used to test the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation feature is enabled.

There are three modes available for LVDS test pattern generation. The mode of test pattern generation is determined by register configuration as shown in the tables below.

Table 7-1 Test Pattern Generation
Test Pattern Generation ModeRegister Configurations
Single LVDS configuration modeLVDS_LINK_CFG(CSR 0x18.4) = 1b
DSI_CH_MODE(CSR 0x10.6:5) = XXb
CHA_TEST_PATTERN(CSR 0x3C.4) = 1b
CHB_TEST_PATTERN(CSR 0x3C.0) = 0b
Dual LVDS configuration modeLVDS_LINK_CFG(CSR 0x18.4) = 0b
DSI_CH_MODE(CSR 0x10.6:5) = 0Xb
CHA_TEST_PATTERN(CSR 0x3C.4) = 1b
CHB_TEST_PATTERN(CSR 0x3C.0) = 0b
Two independent LVDS configuration modeLVDS_LINK_CFG(CSR 0x18.4) = 0b
DSI_CH_MODE(CSR 0x10.6:5) = 10b
CHA_TEST_PATTERN(CSR 0x3C.4) = 1b
CHB_TEST_PATTERN(CSR 0x3C.0) = 1b

The following tables show lists of video registers that need to be configured for test pattern generation video parameters.

  1. Single LVDS configuration
    Table 7-2 Video Registers
    Bit AddressRegister Name
    0x20.7:0CHA_ACTIVE_LINE_LENGTH_LOW
    0x21.3:0CHA_ACTIVE_LINE_LENGTH_HIGH
    0x24.7:0CHA_VERTICAL_DISPLAY_SIZE_LOW
    0x25.3:0CHA_VERTICAL_DISPLAY_SIZE_HIGH
    0x2C.7:0CHA_HSYNC_PULSE_WIDTH_LOW
    0x2D.1:0CHA_HSYNC_PULSE_WIDTH_HIGH
    0x30.7:0CHA_VSYNC_PULSE_WIDTH_LOW
    0x31.1:0CHA_VSYNC_PULSE_WIDTH_HIGH
    0x34.7:0CHA_HORIZONTAL_BACK_PORCH
    0x36.7:0CHA_VERTICAL_BACK_PORCH
    0x38.7:0CHA_HORIZONTAL_FRONT_PORCH
    0x3A.7:0CHA_VERTICAL_FRONT_PORCH
  2. Dual LVDS configuration
    • Same set of video registers are used as in single LVDS configuration.
  3. Two independent LVDS configuration mode.

    Both Channel A and Channel B register parameters need to be configured.

    Table 7-3 Channel A and B Registers
    Bit AddressRegister Name
    Channel A
    0x20.7:0CHA_ACTIVE_LINE_LENGTH_LOW
    0x21.3:0CHA_ACTIVE_LINE_LENGTH_HIGH
    0x24.7:0CHA_VERTICAL_DISPLAY_SIZE_LOW
    0x25.3:0CHA_VERTICAL_DISPLAY_SIZE_HIGH
    0x2C.7:0CHA_HSYNC_PULSE_WIDTH_LOW
    0x2D.1:0CHA_HSYNC_PULSE_WIDTH_HIGH
    0x30.7:0CHA_VSYNC_PULSE_WIDTH_LOW
    0x31.1:0CHA_VSYNC_PULSE_WIDTH_HIGH
    0x34.7:0CHA_HORIZONTAL_BACK_PORCH
    0x36.7:0CHA_VERTICAL_BACK_PORCH
    0x38.7:0CHA_HORIZONTAL_FRONT_PORCH
    0x3A.7:0CHA_VERTICAL_FRONT_PORCH
    Channel B
    0x22.7:0CHB_ACTIVE_LINE_LENGTH_LOW
    0x23.3:0CHB_ACTIVE_LINE_LENGTH_HIGH
    0x26.7:0CHB_VERTICAL_DISPLAY_SIZE_LOW
    0x27.3:0CHB_VERTICAL_DISPLAY_SIZE_HIGH
    0x2E.7:0CHB_HSYNC_PULSE_WIDTH_LOW
    0x2F.1:0CHB_HSYNC_PULSE_WIDTH_HIGH
    0x32.7:0CHB_VSYNC_PULSE_WIDTH_LOW
    0x33.1:0CHB_VSYNC_PULSE_WIDTH_HIGH
    0x35.7:0CHB_HORIZONTAL_BACK_PORCH
    0x37.7:0CHB_VERTICAL_BACK_PORCH
    0x39.7:0CHB_HORIZONTAL_FRONT_PORCH
    0x3B.7:0CHB_VERTICAL_FRONT_PORCH