ZHCSAT8G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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7.5.1 Local I2C Interface Overview

The SN65DSI85 local I2C interface is enabled when EN is input high, access to the CSR registers is supported during ultra-low power state (ULPS). The SCL and SDA terminals are used for I2C clock and I2C data respectively. The SN65DSI85 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN65DSI85 is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 7-6 clarifies the SN65DSI85 target address.

Table 7-6 SN65DSI85 I2C Target Address Description (1) (2)
SN65DSI85 I2C TARGET ADDRESS
BIT 7 (MSB)BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 (W/R)
010110ADDR0/1
(1) When ADDR=1, Address Cycle is 0x5A (Write) and 0x5B (Read)
(2) When ADDR=0, Address Cycle is 0x58 (Write) and 0x59 (Read)

The following procedure is followed to write to the SN65DSI85 I2C registers.

  1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI85 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The SN65DSI85 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within SN65DSI85) to be written, consisting of one byte of data, MSB-first.
  4. The SN65DSI85 acknowledges the sub-address cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The SN65DSI85 acknowledges the byte transfer.
  7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN65DSI85.
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the SN65DSI85 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI85 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  2. The SN65DSI85 acknowledges the address cycle.
  3. The SN65DSI85 transmit the contents of the memory registers MSB-first starting at register 00h. If a write to the SN65DSI85 I2C register occurred prior to the read, then the SN65DSI85 will start at the sub-address specified in the write.
  4. The SN65DSI85 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the SN65DSI85 transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure is followed for setting a starting sub-address for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI85 7-bit address and a zero-value “W/R” bit to indicate a write cycle
  2. The SN65DSI85 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within SN65DSI85) to be written, consisting of one byte of data, MSB-first.
  4. The SN65DSI85 acknowledges the sub-address cycle.
  5. The master terminates the write operation by generating a stop condition (P).