ZHCSAU2G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.1 Control and Status Registers Overview

Many of the SN65DSI84 functions are controlled by the Control and Status Registers (CSR). All CSR registers are accessible through the local I2C interface.

See the following tables for the SN65DSI84 CSR descriptions. Reserved or undefined bit fields should not be modified. Otherwise, the device may operate incorrectly.

Table 5. CSR Bit Field Definitions – ID Registers

ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS(1)
0x00 – 0x08 7:0 Reserved
Addresses 0x08 - 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38, 0x35}		 Reserved RO
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)

Table 6. CSR Bit Field Definitions – Reset and Clock Registers

ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS (1)
0x09 0 SOFT_RESET
This bit automatically clears when set to ‘1’ and returns zeros when read. This bit must be set after the CSR’s are updated. This bit must also be set after making any changes to the DIS clock rate or after changing between DSI burst and non-burst modes.
0 – No action (default)
1 – Reset device to default condition excluding the CSR bits.		 0 WO
0x0A 7 PLL_EN_STAT
0 – PLL not enabled (default)
1 – PLL enabled
Note: After PLL_EN_STAT = 1, wait at least 3ms for PLL to lock.		 0 RO
3:1 LVDS_CLK_RANGE
This field selects the frequency range of the LVDS output clock.
000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz
001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz
010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz
100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz
101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default)
110 – Reserved
111 – Reserved		 101 RW
0 HS_CLK_SRC
0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock		 0 RW
0x0B 7:3 DSI_CLK_DIVIDER
When CSR 0x0A.0 = ‘1’, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = ‘0’, this field must be programmed to 00000.
00000 – LVDS clock = source clock (default)
00001 – Divide by 2
00010 – Divide by 3
00011 – Divide by 4
•
•
•
10111 – Divide by 24
11000 – Divide by 25
11001 through 11111 – Reserved		 00000 RW
1:0 REFCLK_MULTIPLIER
When CSR 0x0A.0 = ‘0’, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = ‘1’, this field must be programmed to 00.
00 – LVDS clock = source clock (default)
01 – Multiply by 2
10 – Multiply by 3
11 – Multiply by 4		 00 RW
0x0D 0 PLL_EN
When this bit is set, the PLL is enabled with the settings programmed into CSR 0x0A and CSR 0x0B. The PLL should be disabled before changing any of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be active and stable before the PLL is enabled.
0 – PLL disabled (default)
1 – PLL enabled		 0 RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)

Table 7. CSR Bit Field Definitions – DSI Registers

ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS (1)
0x10 7 Reserved - Do not write to this field. Must remain at default. 0 RW
6:5 Reserved - Do not write to this field. Must remain at default. 01 RW
4:3 CHA_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel A.
00 – Four lanes are enabled
01 – Three lanes are enabled
10 – Two lanes are enabled
11 – One lane is enabled (default)
Note: Unused DSI input pins on the SN65DSI84 should be left unconnected.		 11 RW
0 SOT_ERR_TOL_DIS
0 – Single bit errors are tolerated for the start of transaction SoT leader sequence (default)
1 – No SoT bit errors are tolerated		 0 RW
0x11 7:6 CHA_DSI_DATA_EQ
This field controls the equalization for the DSI Channel A Data Lanes
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization		 00 RW
3:2 CHA_DSI_CLK_EQ
This field controls the equalization for the DSI Channel A Clock
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization		 00 RW
0x12 7:0 CHA_DSI_CLK_RANGE
This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel A Clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
•
•
•
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved		 0 RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)

Table 8. CSR Bit Field Definitions – LVDS Registers

ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS (1)
0x18 7 DE_NEG_POLARITY
0 – DE is positive polarity driven ‘1’ during active pixel transmission on LVDS (default)
1 – DE is negative polarity driven ‘0’ during active pixel transmission on LVDS		 0 RW
6 HS_NEG_POLARITY
0 – HS is positive polarity driven ‘1’ during corresponding sync conditions
1 – HS is negative polarity driven ‘0’ during corresponding sync (default)		 1 RW
5 VS_NEG_POLARITY
0 – VS is positive polarity driven ‘1’ during corresponding sync conditions
1 – VS is negative polarity driven ‘0’ during corresponding sync (default)		 1 RW
4 LVDS_LINK_CFG

0 – LVDS Channel A and Channel B outputs enabled

When CSR 0x10.6:5 = ’00’ or ‘01’, the LVDS is in Dual-Link configuration

When CSR 0x10.6:5 = ‘10’, the LVDS is in two Single-Link configuration


1 – LVDS Single-Link configuration; Channel A output enabled and Channel B output disabled (default)		 1 RW
3 CHA_24BPP_MODE
0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled		 0 RW
2 CHB_24BPP_MODE
0 – Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled 		0 RW
1 CHA_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel A lane A_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default)
1 – LVDS channel B lane A_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1
Note1: This field must be ‘0’ when 18bpp data is received from DSI.
Note2: If this field is set to ‘1’ and CHA_24BPP_MODE is ‘0’, the SN65DSI84 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI84 will not transmit the 2 LSB per color on LVDS channel A, since LVDS channel A lane A_Y3P/N is disabled.		 0 RW
0 CHB_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel B lane B_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default)
1 – LVDS channel B lane B_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1
Note1: This field must be ‘0’ when 18bpp data is received from DSI.
Note2: If this field is set to ‘1’ and CHB_24BPP_MODE is ‘0’, the SN65DSI84 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI84 will not transmit the 2 LSB per color on LVDS channel B, since LVDS channel B lane B_Y3P/Nis disabled.		 0 RW
0x19 6 CHA_LVDS_VOCM
This field controls the common mode output voltage for LVDS Channel A
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to ‘01b’)		 0 RW
4 CHB_LVDS_VOCM
This field controls the common mode output voltage for LVDS Channel B
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.1:0 CHB_LVDS_CM_ADJUST must be set to ‘01b’)		 0 RW
3:2 CHA_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS Channel A. See the Electrical Characteristics table for |VOD| for each setting:
00, 01 (default), 10, 11. 		01 RW
1:0 CHB_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS Channel B. See the Electrical Characteristics table for |VOD| for each setting:
00, 01 (default), 10, 11. 		01 RW
0x1A 6 EVEN_ODD_SWAP
0 – Odd pixels routed to LVDS Channel A and Even pixels routed to LVDS Channel B (default)
1 – Odd pixels routed to LVDS Channel B and Even pixels routed to LVDS Channel A
Note: When the SN65DSI84 is in two stream mode (CSR 0x10.6:5 = ‘10’), setting this bit to ‘1’ will cause the video stream from DSI Channel A to be routed to LVDS Channel B and the video stream from DSI Channel B to be routed to LVDS Channel A.		 0 RW
5 CHA_REVERSE_LVDS
This bit controls the order of the LVDS pins for Channel A.
0 – Normal LVDS Channel A pin order. LVDS Channel A pin order is the same as listed in the Terminal Assignments Section. (default)

1 – Reversed LVDS Channel A pin order. LVDS Channel A pin order is remapped as follows:

  • A_Y0P → A_Y3P
  • A_Y0N → A_Y3N
  • A_Y1P → A_CLKP
  • A_Y1N → A_CLKN
  • A_Y2P → A_Y2P
  • A_Y2N → A_Y2N
  • A_CLKP → A_Y1P
  • A_CLKN → A_Y1N
  • A_Y3P → A_Y0P
  • A_Y3N → A_Y0N

 0 RW
4 CHB_REVERSE_LVDS
This bit controls the order of the LVDS pins for Channel B.
0 – Normal LVDS Channel B pin order. LVDS Channel B pin order is the same as listed in the Terminal Assignments Section. (default)

1 – Reversed LVDS Channel B pin order. LVDS Channel B pin order is remapped as follows:

  • B_Y0P → B_Y3P
  • B_Y0N → B_Y3N

  • B_Y1P → B_CLKP
  • B_Y1N → B_CLKN
  • B_Y2P → B_Y2P
  • B_Y2N → B_Y2N
  • B_CLKP → B_Y1P
  • B_CLKN → B_Y1N
  • B_Y3P → B_Y0P
  • B_Y3N → B_Y0N

 0 RW
1 CHA_LVDS_TERM
This bit controls the near end differential termination for LVDS Channel A. This bit also affects the output voltage for LVDS Channel A.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)		 1 RW
0 CHB_LVDS_TERM
This bit controls the near end differential termination for LVDS Channel B. This bit also affects the output voltage for LVDS Channel B.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)		 1 RW
0x1B 5:4 CHA_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS Channel A.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%		 00 RW
1:0 CHB_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS Channel B.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%		 00 RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)

Note for all video registers:

  1. TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others are for normal operation unless the test pattern generation feature is enabled.

Table 9. CSR Bit Field Definitions – Video Registers

ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS(1)
0x20 7:0 CHA_ACTIVE_LINE_LENGTH_LOW
This field controls the length in pixels of the active horizontal line line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length.		 0 RW
0x21 3:0 CHA_ACTIVE_LINE_LENGTH_HIGH
This field controls the length in pixels of the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length.		 0 RW
0x24 7:0 CHA_VERTICAL_DISPLAY_SIZE_LOW
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size.		 0 RW
0x25 3:0 CHA_VERTICAL_DISPLAY_SIZE_HIGH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 4 bits of the 12-bit value for the vertical display size		 0 RW
0x28 7:0 CHA_SYNC_DELAY_LOW
This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI84. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the Sync delay.		 0 RW
0x29 3:0 CHA_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI84. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay.		 0 RW
0x2C 7:0 CHA_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 10-bit value for the HSync Pulse Width.		 0 RW
0x2D 1:0 CHA_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 2 bits of the 10-bit value for the HSync Pulse Width.		 0 RW
0x30 7:0 CHA_VSYNC_PULSE_WIDTH_LOW
This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 10-bit value for the VSync Pulse Width.		 0 RW
0x31 1:0 CHA_VSYNC_PULSE_WIDTH_HIGH
This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 2 bits of the 10-bit value for the VSync Pulse Width.		 0 RW
0x34 7:0 CHA_HORIZONTAL_BACK_PORCH
This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).		 0 RW
0x36 7:0 CHA_VERTICAL_BACK_PORCH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).		 0 RW
0x38 7:0 CHA_HORIZONTAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).		 0 RW
0x3A 7:0 CHA_VERTICAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).		 0 RW
0x3C 4 CHA_TEST_PATTERN
TEST PATTERN GENERATION PURPOSE ONLY. When this bit is set, the SN65DSI84 will generate a video test pattern based on the values programmed into the Video Registers for LDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).		 0 RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)

Table 10. CSR Bit Field Definitions – IRQ Registers

ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS (1)
0xE0 0 IRQ_EN
When enabled by this field, the IRQ output is driven high to communicate IRQ events.
0 – IRQ output is high-impedance (default)
1 – IRQ output is driven high when a bit is set in registers 0xE5 that also has the corresponding IRQ_EN bit set to enable the interrupt condition		 0 RW
0xE1 7 CHA_SYNCH_ERR_EN
0 – CHA_SYNCH_ERR is masked
1 – CHA_SYNCH_ERR is enabled to generate IRQ events		 0 RW
6 CHA_CRC_ERR_EN
0 – CHA_CRC_ERR is masked
1 – CHA_CRC_ERR is enabled to generate IRQ events		 0 RW
5 CHA_UNC_ECC_ERR_EN
0 – CHA_UNC_ECC_ERR is masked
1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events		 0 RW
4 CHA_COR_ECC_ERR_EN
0 – CHA_COR_ECC_ERR is masked
1 – CHA_COR_ECC_ERR is enabled to generate IRQ events		 0 RW
3 CHA_LLP_ERR_EN
0 – CHA_LLP_ERR is masked
1 – CHA_ LLP_ERR is enabled to generate IRQ events		 0 RW
2 CHA_SOT_BIT_ERR_EN
0 – CHA_SOT_BIT_ERR is masked
1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events		 0 RW
0 PLL_UNLOCK_EN
0 – PLL_UNLOCK is masked
1 – PLL_UNLOCK is enabled to generate IRQ events		 0 RW
0xE5 7 CHA_SYNCH_ERR
When the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a ‘1’ value.		 0 RW1C
6 CHA_CRC_ERR
When the DSI channel A packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a ‘1’ value.		 0 RW1C
5 CHA_UNC_ECC_ERR
When the DSI channel A packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a ‘1’ value.		 0 RW1C
4 CHA_COR_ECC_ERR
When the DSI channel A packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a ‘1’ value.		 0 RW1C
3 CHA_LLP_ERR
When the DSI channel A packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a ‘1’ value.
Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition.		 0 RW1C
2 CHA_SOT_BIT_ERR
When the DSI channel A packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a ‘1’ value.		 0 RW1C
0 PLL_UNLOCK
This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK.		 1 RW1C
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)