ZHCSES3C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 相关链接
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.1 Layout Guidelines

  • DAxP/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance (± 15%) or 50-Ω single-ended impedance (± 15%).
  • Keep away from other high speed signals.
  • Keep lengths to within 5 mils of each other.
  • Length matching should be near the location of mismatch.
  • Each pair should be separated at least by 3 times the signal trace width.
  • The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and; therefore, minimize the impact bends have on EMI.
  • Route all differential pairs on the same of layer.
  • The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
  • Keep traces on layers adjacent to ground plane.
  • Do NOT route differential pairs over any plane split.
  • Adding Test points will cause impedance discontinuity and will; therefore, negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.