ZHCSND7 September   2022 SN6507-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507-Q1
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

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9.4.1 Layout Guidelines

  • The power supply input, VIN, must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1 μF to 10 μF, and is typically 10 μF. The capacitor must have a voltage rating greater than the VIN voltage level and an X5R or X7R dielectric.
  • The optimum placement of the VIN capacitor is closest to the VIN and GND pins at the board entrance to minimize the loop area formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 9-10 for a PCB layout example.

  • To help ensure reliable operation, a 0.1-μF low-ESR ceramic bypass-capacitor is recommended at the device VCC pin. The capacitor should be placed as close to the supply pins as possible in the PCB layout and on the same layer. The capacitor must have a voltage rating greater than the VIN voltage level.

  • The connections between the device SW1 and SW2 pins and the transformer primary endings and the connection of the device VCC pin and the transformer center-tap must be as short as possible for minimum trace inductance.
  • The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF, and is typically 10 μF. The capacitor must have a voltage rating greater than the VIN voltage level and an X5R or X7R dielectric.
  • The device GND pins must be tied to the PCB ground plane using two vias to help minimize inductance.
  • The ground connections of the capacitors and other connections to the ground plane should use two vias for minimum inductance.
  • The rectifier diodes should be Schottky diodes with low forward voltage and low capacitance to maximize efficiency.
  • The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The typical capacitor value can range from 500 nF to 10 μF and should be less than 10 times the value of CSS to ensure a smooth transition between soft-start and the steady state.