ZHCSNB2 February   2021 SN55LVCP22A-SP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Select Pins
      2. 8.3.2 Output Enable Pins
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Current-Mode Logic (CML)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Single-Ended (LVPECL)
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Low-Voltage Differential Signaling (LVDS)
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Cold Sparing
      6. 9.2.6 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.6 Switching Characteristics

over recommended operating conditions unless otherwise noted
parameter TEST CONDITIONS MIN TYP MAX UNIT
tSET Input to SEL setup time See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDIOZO-9FXRHU 0.8 2.2 ns
tHOLD Input to SEL hold time See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDIOZO-9FXRHU 1.0 2.2 ns
tSWITCH SEL to switched output See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDIOZO-9FXRHU 1.7 2.6 ns
tPHZ Disable time, high-level-to-high-impedance See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDPPZO-21CXRHU 2 8 ns
tPLZ Disable time, low-level-to-high-impedance See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDPPZO-21CXRHU 2 8 ns
tPZH Enable time, high-impedance -to-high-level output See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDPPZO-21CXRHU 2 8 ns
tPZL Enable time, high-impedance-to-low-level output See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDPPZO-21CXRHU 2 8 ns
tLHT Differential output signal rise time (20%-80%)#IDHYWK-35FX000 CL = 5 pF, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDBRZO-B2XRHU 280 620 ps
tHLT Differential output signal fall time (20%-80%)#IDHYWK-35FX000 CL = 5 pF, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDBRZO-B2XRHU 280 620 ps
tJIT Added peak-to-peak jitter#SLLSE437856 VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 50 MHz, CL = 5 pF		 13.7 22.2 ps
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF		 13.4 24.5
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF		 14.4 35.7
VID = 200 mV, PRBS = 215-1 data pattern,
VCM = 1.2 V, 240 Mbps, CL = 5 pF		 68.3 204 ps
VID = 200 mV, PRBS = 215-1 data pattern,
VCM = 1.2 V, 1000 Mbps, CL = 5 pF		 73.2 282
tJrms Added random jitter (rms)#SLLSE437856 VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 50 MHz, CL = 5 pF		 0.97 1.5 psRMS
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF		 0.85 1.53
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF		 0.86 1.79
tPLHD Propagation delay time, low-to-high-level output#IDHYWK-35FX000 200 650 2350 ps
tPHLD Propagation delay time, high-to-low-level output#IDHYWK-35FX000 200 650 2350 ps
tskew #IDHJWER1234564 Pulse skew (|tPLHD – tPHLD|)#IDGIBUY26CA075 CL = 5 pF, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDBRZO-B2XRHU 45 160 ps
tCCS Output channel-to-channel skew, splitter mode CL = 5 pF, See GUID-DFC33E3A-CD0C-47EA-9546-39403915B952.html#IDBRZO-B2XRHU 80 ps
fMAX #IDHJWER1234564 Maximum operating frequency#IDOYQX-289X000 1 GHz
(1) Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps
(2) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
(3) Not production tested.
(4) Signal generator conditions: 50% duty cycle, tr or tf ≤ 100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD ≥ 300 mV.
(5) tskew and fMAX parameters are guaranteed by characterization, but not production tested.