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ZHCSFA5 July 2016 SM320C6457-HIREL

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4 Specifications

4.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
Supply voltage⁽²⁾	CV_DD		–0.3	1.35	V
	DV_DD18		–0.3	2.45
	DV_DD33		–0.3	3.6
	V_REFSSTL		0.49 × DV_DD18	0.51 × DV_DD18
	V_DD11, V_DDD11, V_DDT11		–0.3	1.35
	V_DDR18		–0.3	2.45
	AV_DD118, AV_DD218		–0.3	2.45
	V_SS ground		0
Input voltage, V_I	LVCMOS (1.8 V)		–0.3	DV_DD18 + 0.3	V
	LVCMOS (3.3 V)		–0.3	DV_DD33 + 0.3
	DDR2		–0.3	2.45
	I²C		–0.3	2.45
	LVDS		–0.3	D_VDD18+ 0.3
	LJCB		–0.3	1.35
	SerDes		–0.3	D_VDD11 + 0.3
Output voltage, V_O	LVCMOS (1.8 V)		–0.3	DV_DD18 + 0.3	V
	LVCMOS (3.3 V)		–0.3	DV_DD33+ 0.3
	DDR2		–0.3	2.45
	I²C		–0.3	2.45
	SerDes		–0.3	DV_DD11 + 0.3
Operating case temperature, T_C	Extended	1-GHz CPU	–55	100	°C
Overshoot/undershoot⁽³⁾	LVCMOS (1.8 V)		20% overshoot/undershoot for 20% of signal duty cycle		V
	LVCMOS (3.3 V)
	DDR2
	I²C
Storage temperature, T_stg			–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS.

(3) Overshoot/undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DV_DD18 + 0.2 × DV_DD18and maximum undershoot value would be V_SS - 0.2 × DV_DD18

4.2 ESD Ratings

			VALUE		UNIT
V_ESD	ESD stress voltage⁽¹⁾	Human-body model (HBM)⁽²⁾	±1000		V
V_ESD	ESD stress voltage⁽¹⁾	Charged-device model (CDM)⁽³⁾⁽⁴⁾	±500		V

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP 155 states that 500V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary precautions are taken. Pins listed as 1000V may actually have higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP 157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.

(4) Based on JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components), the C6457 device’s charged-device model (CDM) sensitivity classification is Class II (200 V to < 500 V). Specifically, DDR memory interface and SerDes pins conform to ±200-V level. All other pins conform to ±500 V.

4.3 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
CV_DD	Supply core voltage		850-MHz CPU	1.067	1.1	1.133	V
CV_DD	Supply core voltage		1-GHz CPU	1.067	1.1	1.133	V
DV_DD18	1.8-V supply I/O voltage			1.71	1.8	1.89	V
DV_DD33	3.3-V supply I/O voltage			3.135	3.3	3.465	V
V_REFSSTL	DDR2 reference voltage			0.49 × DV_DD18	0.5 × DV_DD18	0.51 × DV_DD18	V
V_DDR18	SRIO/SGMII SerDes regulator supply			1.71	1.8	1.89	V
V_DDA11	SRIO/SGMII SerDes analog supply			1.045	1.1	1.155	V
V_DDD11	SRIO/SGMII SerDes digital supply			1.045	1.1	1.155	V
V_DDT11	SRIO/SGMII SerDes termination supply			1.045	1.1	1.155	V
PLLV₁	PLL1 analog supply			1.71	1.8	1.89	V
PLLV₂	PLL2 analog supply			1.71	1.8	1.89	V
V_SS	Ground			0	0	0	V
V_IH	High-level input voltage	LVCMOS (1.8 V)		0.65 × DV_DD18			V
		LVCMOS (3.3 V)		2			V
		I²C		0.7 × DV_DD18			V
		DDR2 EMIF		V_REFSSTL + 0.125		DV_DD18 + 0.3	V
V_IL	Low-level input voltage	LVCMOS (1.8 V)				0.35 × DV_DD18	V
		LVCMOS (3.3 V)				0.8	V
		DDR2 EMIF		-0.3		V_REFSSTL – 0.1	V
		I²C				0.3 × DV_DD18	V
T_C	Operating case temperature	Extended	1-GHz CPU	–55		100	°C

(1) All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

4.4 Electrical Characteristics

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER			TEST CONDITIONS⁽¹⁾	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	LVCMOS (1.8 V)	I_O = I_OH	DV_DD18 – 0.45			V
		LVCMOS (3.3 V)	I_O= -2 mA	2.4
		DDR2		1.4
		I²C		0.1 × DV_DD18
V_OL	Low-level output voltage	LVCMOS (1.8 V)	I_O = I_OL			0.45	V
		LVCMOS (3.3 V)	I_O= 2 mA			0.4
		DDR2				0.4
		I²C	I_O = 3 mA, pulled up to 1.8 V			0.4
I_I⁽²⁾	Input current [DC]	LVCMOS (1.8 V)	No IPD/IPU	–5		5	µA
			Internal pullup	50	100	170
			Internal pulldown	–170	-100	-50
		LVCMOS (3.3 V)	No IPD/IPU	–1		1
			Internal pullup	70	150	270
			Internal pulldown	–270	–150	–70
		I²C	0.1 × DV_DD18 V < V_I < 0.9 × DV_DD18 V	–20		20
I_OH	High-level output current [DC]	EMU[18:00], GPIO[15:0], TIMO[1:0]				–8	mA
		SYSCLKOUT, TDO, CLKR0, CLKX0, DX0, FSR0, FSX0, CLKR1, CLKX1, DX1, FSR1, FSX1, AECLKOUT				–6
		RESETSTAT, MDIO, MDCLK				–4
		DDR2				4
		LVCMOS (3.3 V), except AECLKOUT				–4
I_OL	Low-level output current [DC]	EMU[18:00], GPIO[15:0], TIM[1:0]				8	mA
		SYSCLKOUT, TDO, CLKR0, CLKX0, DX0, FSR0, FSX0, CLKR1, CLKX1, DX1, FSR1, FSX1, AECLKOUT				6
		RESETSTAT, MDIO, MDCLK				4
		DDR2				–4
		LVCMOS (3.3 V), except AECLKOUT				4
I_OZ⁽³⁾	Off-state output current [DC]	LVCMOS (1.8 V)		–20		20	µA
I_OZ⁽³⁾	Off-state output current [DC]	LVCMOS (3.3 V)		–20		20	µA

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(2) I_I applies to input-only pins and bi-directional pins. For input-only pins, I_I indicates the input leakage current. For bi-directional pins, I_Iincludes input leakage current and off-state (Hi-Z) output leakage current.

(3) I_OZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

4.5 Thermal Resistance Characteristics

Table 4-1 shows the thermal resistance characteristics for the PBGA - GMH mechanical package.

Table 4-1 Thermal Resistance Characteristics GMH Package

NO.			°C/W
1	Rθ_JC	Junction-to-case	1.53
2	Rθ_JB	Junction-to-board	8.1

4.6 Timing and Switching Characteristics

4.6.1 Timing Parameters and Information

This section describes the conditions used to capture the electrical data seen in this chapter.

SM320C6457-HIREL Test_Load_Circuit_for_AC_Timing_Measurements_6484.gif

Figure 4-1 Test Load Circuit for AC Timing Measurements

(A) The data manual provides timing at the device terminal. For output timing analysis, the tester terminal electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

(B) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device terminal.

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

4.6.1.1 1.8-V Signal Transition Levels

All input and output timing parameters are referenced to 0.9 V for both 0 and 1 logic levels.

SM320C6457-HIREL Input_and_Output_Voltage_Ref_Levels_for_1.8-V_AC_Timing_6484.gif

Figure 4-2 Input and Output Voltage Reference Levels for 1.8-V AC Timing Measurements

All rise and fall transition timing parameters are reference to V_IL MAX and V_IH MIN for input clocks.

SM320C6457-HIREL rise_fall_transition_time.gif

Figure 4-3 Rise and Fall Transition Time Voltage Reference Levels

4.6.1.2 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.

SM320C6457-HIREL Input_and_Output_Voltage_Ref_Levels_for_3.3-V_AC_Timing_6484.gif

Figure 4-4 Input and Output Voltage Reference Levels for 3.3-V AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OLMAX and V_OH MIN for output clocks.

Figure 4-5 Rise and Fall Transition Time Voltage Reference Levels

4.6.1.3 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

4.6.1.4 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 4-2 and Figure 4-6).

Table 4-2 Board-Level Timing Example

(see Figure 4-6)

NO.	DESCRIPTION
1	Clock route delay
2	Minimum DSP hold time
3	Minimum DSP setup time
4	External device hold time requirement
5	External device setup time requirement
6	Control signal route delay
7	External device hold time
8	External device access time
9	DSP hold time requirement
10	DSP setup time requirement
11	Data route delay

Figure 4-6 shows a general transfer between the DSP and an external device. The figure also shows board route delays and how they are perceived by the DSP and the external device

SM320C6457-HIREL Board_Level_Input_Output_Timings_6484.gif

Figure 4-6 Board-Level Input/Output Timings

(A) Control signals include data for writes.

(B) Data signals are generated during reads from an external device.

4.6.2 Power Supply Sequencing

The following sections describe the proper power-supply sequencing and timing needed to properly power on the C6457 DSP. This section also describes proper power-supply decoupling methods.

TI recommends the power-supply sequence shown in Figure 4-7 and described in Table 4-3. The figure shows that the 1.8-V I/O supply should be ramped first. This is followed by the scaled core supply and the fixed 1.1-V supplies which must ramp within 5 ms of each other. The 3.3-V I/O supply should ramp up last. Some TI power supply devices include features that facilitate power sequencing; for example, Auto-Track or Slow-Start/Enable features. For more information, visit www.ti.com/dsppower. See the TMS320TCI6468 and TMS329C6457 DSPs Hardware Design Guide (SPRAAV7) for further details on proper power-supply sequencing.

SM320C6457-HIREL Power_Supply_Sequence_6484.gif

Figure 4-7 Power Supply Sequence

Table 4-3 Timing Requirements for Power Supply Sequence

NO.			MIN	MAX	UNIT
1	t_{su(DVDD18-DVDD11)}	Setup Time, DV_DD18 and V_REFSSTL supplies stable before DV_DD11 and CV_DD11 supplies stable	0.5	200	ms
2	t_{su(DVDD11-DVDD33)}	Setup Time, DV_DD11 and CV_DD11 supplies stable before DV_DD33 supply stable	0.5	200	ms
3	t_h(DVDD33-_POR)	Hold time, POR low after DV_DD33 supplies stable	100		µs

4.6.2.1 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered.

4.6.2.2 Power-Down Operation

One of the power goals for the C6457 is to reduce power dissipation due to unused peripherals. There are different ways to power down peripherals on the device.

After device reset, all peripherals on the C6457 device are in a disabled state and must be enabled by software before being used. It is possible to enable only the peripherals needed by the application while keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks gated. For more information on how to enable peripherals, see Section 5.5.2

Peripherals used for booting, like I²C and HPI, are automatically enabled after device reset. It is possible to disable peripherals used for booting after the boot process is complete. This, too, results in gating of the clock(s) to the powered-down peripheral. Once a peripheral is powered-down, it must remain powered down until the next device reset.

The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+ megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or the entire C64x+ megamodule through the power-down controller based on its own execution thread or in response to an external stimulus from a host or global controller. More information on the power-down features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (SPRU871).

4.6.2.3 Power Supply to Peripheral I/O Mapping

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

POWER SUPPLY		I/O BUFFER TYPE	ASSOCIATED PERIPHERAL
CV_DD	Supply core voltage	LJCB	CORECLK(P\|N) PLL input buffers
			DDRREFCLK(N\|P) PLL input buffers
			RIOSGMIICLK(N\|P) SERDES PLL input buffers
DV_DD18	1.8-V supply I/O voltage	LVCMOS (1.8 V)	ALTCORECLK PLL input buffer
			ALTDDRCLK PLL input buffer
			POR/RESET input buffers
			All GPIO peripheral I/O buffer
			All McBSP0/McBSP1 peripheral I/O buffer
			All MDIO peripheral I/O buffer
			All Timer0/Timer1 peripheral I/O buffer
			NMI input buffers
		DDR2 (1.8V)	All DDR2 memory controller peripheral I/O buffer
		Open-drain (1.8 V)	All I²C peripheral I/O buffer
DV_DD33	3.3-V supply I/O voltage	LVCMOS (3.3 V)	All EMIFA peripheral I/O buffer
			ALL HPI peripheral I/O buffer
			ALL UTOPIA peripheral I/O buffer
V_DDA11	SRIO/SGMII SerDes analog supply	CML	SRIO/SGMII SerDes CML I/O buffer

(1) Please see the TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (SPRAAV7) for more information about individual peripheral I/O.

4.6.3 Reset Timing

Table 4-4 Reset Timing Requirements⁽¹⁾⁽²⁾

(see Figure 4-8 and Figure 4-9)

NO.			MIN	UNIT
1	t_{h(SUPPLY-POR)}	Hold Time, POR low after supplies stable and input clocks valid	1000	ns
2	t_{su(RESETH-PORH)}	Setup Time, RESET high to POR high	1000	ns
4	t_w(RESET)	Pulse Duration, RESET low	24C	ns
7	t_s(BOOT)	Setup time, boot mode and configuration pins valid before POR or RESET high	12C	ns
8	t_h(BOOT)	Hold time, bootmode and configuration pins valid after POR or RESET high	12C	ns

(1) If CORECLKSEL = 0, C = 1 ÷ CORECLK(N|P) frequency in ns.

(2) If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency in ns.

Table 4-5 Reset Switching Characteristics Over Recommended Operating Conditions

(see Figure 4-8 and Figure 4-9)

NO.	PARAMETER		MIN	MAX	UNIT
3	t_{d(PORH-RSTATH)}	Delay Time, POR high to RESETSTAT high		200	µs
5	t_{d(RESETH-RSTATH)}	Delay Time, RESET high to RESETSTAT high		5	µs

Table 4-6 Warm Reset Switching Characteristics Over Recommended Operating Conditions

(see Figure 4-9 and Figure 4-10)

NO.	PARAMETER		MIN	MAX	UNIT
9	t_{su(PORH-RESETL)}	Setup time, POR high to RESET low	1.34		ns

SM320C6457-HIREL Power_On_Reset_Timing_6484.gif

Figure 4-8 Power-On Reset Timing

SM320C6457-HIREL warm_reset_resetstat.gif

Figure 4-9 Warm Reset Timing — RESETSTAT Relative to RESET

SM320C6457-HIREL warm_reset_setup_time.gif

Figure 4-10 Warm Reset Timing — Setup Time Between POR De-Asserted and RESET Asserted

4.6.4 Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic manner.

4.7 Peripherals

This section describes the various peripherals on the C6457 DSP. Peripheral specific information, timing diagrams, electrical specifications and register memory maps are described in this chapter.

4.7.1 Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event-driven peripherals such as a McBSP or the UTOPIA port, and offloads data transfers from the device CPU.

The EDMA3 includes the following features:

Fully orthogonal transfer description
- 3 transfer dimensions:
  - Array (multiple bytes)
  - Frame (multiple arrays)
  - Block (multiple frames)
- Single event can trigger transfer of array, frame, or entire block
- Independent indexes on source and destination
Flexible transfer definition:
- Increment or FIFO transfer addressing modes
- Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention
- Chaining allows multiple transfers to execute with one event
256 PaRAM entries
- Used to define transfer context for channels
- Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
64 DMA channels
- Manually triggered (CPU writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another)
8 Quick DMA (QDMA) channels
- Used for software-driven transfers
- Triggered upon writing to a single PaRAM set entry
6 transfer controllers and 6 event queues with programmable system-level priority
Interrupt generation for transfer completion and error conditions
Debug visibility
- Queue watermarking/threshold allows detection of maximum usage of event queues
- Error and status recording to facilitate debug

Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 5-20 lists the peripherals that can be accessed by the transfer controllers.

4.7.1.1 EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used. On the C6457 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder Coprocessor (VCP2) and the Enhanced Turbo Decoder Coprocessor (TCP2). Constant addressing mode is not supported by any other peripheral or internal memory in the C6457 DSP. Note that increment mode is supported by all C6457 peripherals, including VCP2 and TCP2. For more information on these two addressing modes, see the TMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's Guide (SPRUGK6).

A DSP interrupt must be generated at the end of an HPI boot operation to begin execution of the loaded application. Because the DSP interrupt generated by the HPI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0. The EDMA3 on the C6457 DSP supports active memory protection, but it does not support proxied memory protection.

4.7.1.2 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. Table 4-7 lists the source of the synchronization event associated with each of the DMA channels. On the C6457, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see theTMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's Guide (SPRUGK6).

Table 4-7 C6457 EDMA3 Channel Synchronization Events⁽¹⁾

EDMA CHANNEL	EVENT NAME	EVENT DESCRIPTION
0⁽²⁾	DSP_EVT	HPI-to-DSP event
1	TEVTLO0	Timer 0 Lower Counter Event
2	TEVTHI0	Timer 0 High Counter Event
3 - 8	-	None
9	ETBHFULLINT	Embedded Trace Buffer (ETB) is half full
10	ETBFULLINT	Embedded Trace Buffer (ETB) is full
11	ETBACQINT	Embedded Trace Buffer (ETB) acquisition is complete
12	XEVT0	McBSP0 Transmit Event
13	REVT0	McBSP0 Receive Event
14	XEVT1	McBSP1 Transmit Event
15	REVT1	McBSP1 Receive Event
16	TEVTLO1	Timer 1 Lower Counter Event
17	TEVTHI1	Timer 1 High Counter Event
18	-	None
19	INTDST0	RapidIO Interrupt 0
20	INTDST1	RapidIO Interrupt 1
21	INTDST2	RapidIO Interrupt 2
22	INTDST3	RapidIO Interrupt 3
23	INTDST4	RapidIO Interrupt 4
24	INTDST5	RapidIO Interrupt 5
25	INTDST6	RapidIO Interrupt 6
26 - 27	-	None
28	VCP2REVT	VCP2 Receive Event
29	VCP2XEVT	VCP2 Transmit Event
30	TCP2AREVT	TCP2_A Receive Event
31	TCP2AXEVT	TCP2_A Transmit Event
32	UREVT	UTOPIA Receive Event
33	TCP2BREVT	TCP2_B Receive Event
34	TCP2BXEVT	TCP2_B Transmit Event
35 - 39	-	None
40	UXEVT	UTOPIA Transmit Event
41 - 43	-	None
44	ICREVT	I²C Receive Event
45	ICXEVT	I²C Transmit Event
46 - 47	-	None
48	GPINT0	GPIO event 0
49	GPINT1	GPIO event 1
50	GPINT2	GPIO event 2
51	GPINT3	GPIO event 3
52	GPINT4	GPIO event 4
53	GPINT5	GPIO event 5
54	GPINT6	GPIO event 6
55	GPINT7	GPIO event 7
56	GPINT8	GPIO event 8
57	GPINT9	GPIO event 9
58	GPINT10	GPIO event 10
59	GPINT11	GPIO event 11
60	GPINT12	GPIO event 12
61	GPINT13	GPIO event 13
62	GPINT14	GPIO event 14
63	GPINT15	GPIO event 15

(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see theTMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's Guide (SPRUGK6).

(2) HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.

4.7.1.3 EDMA3 Peripheral Register Description(s)

Table 4-8 EDMA3 Registers

HEX ADDRESS	ACRONYM	REGISTER NAME
02A0 0000	PID	Peripheral ID Register
02A0 0004	CCCFG	EDMA3CC Configuration Register
02A0 0008 - 02A0 00FC	-	Reserved
02A0 0100	DCHMAP0	DMA Channel 0 Mapping Register
02A0 0104	DCHMAP1	DMA Channel 1 Mapping Register
02A0 0108	DCHMAP2	DMA Channel 2 Mapping Register
02A0 010C	DCHMAP3	DMA Channel 3 Mapping Register
02A0 0110	DCHMAP4	DMA Channel 4 Mapping Register
02A0 0114	DCHMAP5	DMA Channel 5 Mapping Register
02A0 0118	DCHMAP6	DMA Channel 6 Mapping Register
02A0 011C	DCHMAP7	DMA Channel 7 Mapping Register
02A0 0120	DCHMAP8	DMA Channel 8 Mapping Register
02A0 0124	DCHMAP9	DMA Channel 9 Mapping Register
02A0 0128	DCHMAP10	DMA Channel 10 Mapping Register
02A0 012C	DCHMAP11	DMA Channel 11 Mapping Register
02A0 0130	DCHMAP12	DMA Channel 12 Mapping Register
02A0 0134	DCHMAP13	DMA Channel 13 Mapping Register
02A0 0138	DCHMAP14	DMA Channel 14 Mapping Register
02A0 013C	DCHMAP15	DMA Channel 15 Mapping Register
02A0 0140	DCHMAP16	DMA Channel 16 Mapping Register
02A0 0144	DCHMAP17	DMA Channel 17 Mapping Register
02A0 0148	DCHMAP18	DMA Channel 18 Mapping Register
02A0 014C	DCHMAP19	DMA Channel 19 Mapping Register
02A0 0150	DCHMAP20	DMA Channel 20 Mapping Register
02A0 0154	DCHMAP21	DMA Channel 21 Mapping Register
02A0 0158	DCHMAP22	DMA Channel 22 Mapping Register
02A0 015C	DCHMAP23	DMA Channel 23 Mapping Register
02A0 0160	DCHMAP24	DMA Channel 24 Mapping Register
02A0 0164	DCHMAP25	DMA Channel 25 Mapping Register
02A0 0168	DCHMAP26	DMA Channel 26 Mapping Register
02A0 016C	DCHMAP27	DMA Channel 27 Mapping Register
02A0 0170	DCHMAP28	DMA Channel 28 Mapping Register
02A0 0174	DCHMAP29	DMA Channel 29 Mapping Register
02A0 0178	DCHMAP30	DMA Channel 30 Mapping Register
02A0 017C	DCHMAP31	DMA Channel 31 Mapping Register
02A0 0180	DCHMAP32	DMA Channel 32 Mapping Register
02A0 0184	DCHMAP33	DMA Channel 33 Mapping Register
02A0 0188	DCHMAP34	DMA Channel 34 Mapping Register
02A0 018C	DCHMAP35	DMA Channel 35 Mapping Register
02A0 0190	DCHMAP36	DMA Channel 36 Mapping Register
02A0 0194	DCHMAP37	DMA Channel 37 Mapping Register
02A0 0198	DCHMAP38	DMA Channel 38 Mapping Register
02A0 019C	DCHMAP39	DMA Channel 39 Mapping Register
02A0 01A0	DCHMAP40	DMA Channel 40 Mapping Register
02A0 01A4	DCHMAP41	DMA Channel 41 Mapping Register
02A0 01A8	DCHMAP42	DMA Channel 42 Mapping Register
02A0 01AC	DCHMAP43	DMA Channel 43 Mapping Register
02A0 01B0	DCHMAP44	DMA Channel 44 Mapping Register
02A0 01B4	DCHMAP45	DMA Channel 45 Mapping Register
02A0 01B8	DCHMAP46	DMA Channel 46 Mapping Register
02A0 01BC	DCHMAP47	DMA Channel 47 Mapping Register
02A0 01C0	DCHMAP48	DMA Channel 48 Mapping Register
02A0 01C4	DCHMAP49	DMA Channel 49 Mapping Register
02A0 01C8	DCHMAP50	DMA Channel 50 Mapping Register
02A0 01CC	DCHMAP51	DMA Channel 51 Mapping Register
02A0 01D0	DCHMAP52	DMA Channel 52 Mapping Register
02A0 01D4	DCHMAP53	DMA Channel 53 Mapping Register
02A0 01D8	DCHMAP54	DMA Channel 54 Mapping Register
02A0 01DC	DCHMAP55	DMA Channel 55 Mapping Register
02A0 01E0	DCHMAP56	DMA Channel 56 Mapping Register
02A0 01E4	DCHMAP57	DMA Channel 57 Mapping Register
02A0 01E8	DCHMAP58	DMA Channel 58 Mapping Register
02A0 01EC	DCHMAP59	DMA Channel 59 Mapping Register
02A0 01F0	DCHMAP60	DMA Channel 60 Mapping Register
02A0 01F4	DCHMAP61	DMA Channel 61 Mapping Register
02A0 01F8	DCHMAP62	DMA Channel 62 Mapping Register
02A0 01FC	DCHMAP63	DMA Channel 63 Mapping Register
02A0 0200	QCHMAP0	QDMA Channel 0 Mapping Register
02A0 0204	QCHMAP1	QDMA Channel 1 Mapping Register
02A0 0208	QCHMAP2	QDMA Channel 2 Mapping Register
02A0 020C	QCHMAP3	QDMA Channel 3 Mapping Register
02A0 0210	QCHMAP4	QDMA Channel 4 Mapping Register
02A0 0214	QCHMAP5	QDMA Channel 5 Mapping Register
02A0 0218	QCHMAP6	QDMA Channel 6 Mapping Register
02A0 021C	QCHMAP7	QDMA Channel 7 Mapping Register
02A0 0220 - 02A0 023C	-	Reserved
02A0 0240	DMAQNUM0	DMA Queue Number Register 0
02A0 0244	DMAQNUM1	DMA Queue Number Register 1
02A0 0248	DMAQNUM2	DMA Queue Number Register 2
02A0 024C	DMAQNUM3	DMA Queue Number Register 3
02A0 0250	DMAQNUM4	DMA Queue Number Register 4
02A0 0254	DMAQNUM5	DMA Queue Number Register 5
02A0 0258	DMAQNUM6	DMA Queue Number Register 6
02A0 025C	DMAQNUM7	DMA Queue Number Register 7
02A0 0260	QDMAQNUM	QDMA Queue Number Register
02A0 0264 - 02A0 027C	-	Reserved
02A0 0280	QUETCMAP	Queue to TC Mapping Register
02A0 0284	QUEPRI	Queue Priority Register
02A0 0288 - 02A0 02FC	-	Reserved
02A0 0300	EMR	Event Missed Register
02A0 0304	EMRH	Event Missed Register High
02A0 0308	EMCR	Event Missed Clear Register
02A0 030C	EMCRH	Event Missed Clear Register High
02A0 0310	QEMR	QDMA Event Missed Register
02A0 0314	QEMCR	QDMA Event Missed Clear Register
02A0 0318	CCERR	EDMA3CC Error Register
02A0 031C	CCERRCLR	EDMA3CC Error Clear Register
02A0 0320	EEVAL	Error Evaluate Register
02A0 0324 - 02A0 033C	-	Reserved
02A0 0340	DRAE0	DMA Region Access Enable Register for Region 0
02A0 0344	DRAEH0	DMA Region Access Enable Register High for Region 0
02A0 0348	DRAE1	DMA Region Access Enable Register for Region 1
02A0 034C	DRAEH1	DMA Region Access Enable Register High for Region 1
02A0 0350	DRAE2	DMA Region Access Enable Register for Region 2
02A0 0354	DRAEH2	DMA Region Access Enable Register High for Region 2
02A0 0358	DRAE3	DMA Region Access Enable Register for Region 3
02A0 035C	DRAEH3	DMA Region Access Enable Register High for Region 3
02A0 0360	DRAE4	DMA Region Access Enable Register for Region 4
02A0 0364	DRAEH4	DMA Region Access Enable Register High for Region 4
02A0 0368	DRAE5	DMA Region Access Enable Register for Region 5
02A0 036C	DRAEH5	DMA Region Access Enable Register High for Region 5
02A0 0370	DRAE6	DMA Region Access Enable Register for Region 6
02A0 0374	DRAEH6	DMA Region Access Enable Register High for Region 6
02A0 0378	DRAE7	DMA Region Access Enable Register for Region 7
02A0 037C	DRAEH7	DMA Region Access Enable Register High for Region 7
02A0 0380	QRAE0	QDMA Region Access Enable Register for Region 0
02A0 0384	QRAE1	QDMA Region Access Enable Register for Region 1
02A0 0388	QRAE2	QDMA Region Access Enable Register for Region 2
02A0 038C	QRAE3	QDMA Region Access Enable Register for Region 3
02A0 0390	QRAE4	QDMA Region Access Enable Register for Region 4
02A0 0394	QRAE5	QDMA Region Access Enable Register for Region 5
02A0 0398	QRAE6	QDMA Region Access Enable Register for Region 6
02A0 039C	QRAE7	QDMA Region Access Enable Register for Region 7
02A0 0400	Q0E0	Event Queue 0 Entry Register 0
02A0 0404	Q0E1	Event Queue 0 Entry Register 1
02A0 0408	Q0E2	Event Queue 0 Entry Register 2
02A0 040C	Q0E3	Event Queue 0 Entry Register 3
02A0 0410	Q0E4	Event Queue 0 Entry Register 4
02A0 0414	Q0E5	Event Queue 0 Entry Register 5
02A0 0418	Q0E6	Event Queue 0 Entry Register 6
02A0 041C	Q0E7	Event Queue 0 Entry Register 7
02A0 0420	Q0E8	Event Queue 0 Entry Register 8
02A0 0424	Q0E9	Event Queue 0 Entry Register 9
02A0 0428	Q0E10	Event Queue 0 Entry Register 10
02A0 042C	Q0E11	Event Queue 0 Entry Register 11
02A0 0430	Q0E12	Event Queue 0 Entry Register 12
02A0 0434	Q0E13	Event Queue 0 Entry Register 13
02A0 0438	Q0E14	Event Queue 0 Entry Register 14
02A0 043C	Q0E15	Event Queue 0 Entry Register 15
02A0 0440	Q1E0	Event Queue 1 Entry Register 0
02A0 0444	Q1E1	Event Queue 1 Entry Register 1
02A0 0448	Q1E2	Event Queue 1 Entry Register 2
02A0 044C	Q1E3	Event Queue 1 Entry Register 3
02A0 0450	Q1E4	Event Queue 1 Entry Register 4
02A0 0454	Q1E5	Event Queue 1 Entry Register 5
02A0 0458	Q1E6	Event Queue 1 Entry Register 6
02A0 045C	Q1E7	Event Queue 1 Entry Register 7
02A0 0460	Q1E8	Event Queue 1 Entry Register 8
02A0 0464	Q1E9	Event Queue 1 Entry Register 9
02A0 0468	Q1E10	Event Queue 1 Entry Register 10
02A0 046C	Q1E11	Event Queue 1 Entry Register 11
02A0 0470	Q1E12	Event Queue 1 Entry Register 12
02A0 0474	Q1E13	Event Queue 1 Entry Register 13
02A0 0478	Q1E14	Event Queue 1 Entry Register 14
02A0 047C	Q1E15	Event Queue 1 Entry Register 15
02A0 0480	Q2E0	Event Queue 2 Entry Register 0
02A0 0484	Q2E1	Event Queue 2 Entry Register 1
02A0 0488	Q2E2	Event Queue 2 Entry Register 2
02A0 048C	Q2E3	Event Queue 2 Entry Register 3
02A0 0490	Q2E4	Event Queue 2 Entry Register 4
02A0 0494	Q2E5	Event Queue 2 Entry Register 5
02A0 0498	Q2E6	Event Queue 2 Entry Register 6
02A0 049C	Q2E7	Event Queue 2 Entry Register 7
02A0 04A0	Q2E8	Event Queue 2 Entry Register 8
02A0 04A4	Q2E9	Event Queue 2 Entry Register 9
02A0 04A8	Q2E10	Event Queue 2 Entry Register 10
02A0 04AC	Q2E11	Event Queue 2 Entry Register 11
02A0 04B0	Q2E12	Event Queue 2 Entry Register 12
02A0 04B4	Q2E13	Event Queue 2 Entry Register 13
02A0 04B8	Q2E14	Event Queue 2 Entry Register 14
02A0 04BC	Q2E15	Event Queue 2 Entry Register 15
02A0 04C0	Q3E0	Event Queue 3 Entry Register 0
02A0 04C4	Q3E1	Event Queue 3 Entry Register 1
02A0 04C8	Q3E2	Event Queue 3 Entry Register 2
02A0 04CC	Q3E3	Event Queue 3 Entry Register 3
02A0 04D0	Q3E4	Event Queue 3 Entry Register 4
02A0 04D4	Q3E5	Event Queue 3 Entry Register 5
02A0 04D8	Q3E6	Event Queue 3 Entry Register 6
02A0 04DC	Q3E7	Event Queue 3 Entry Register 7
02A0 04E0	Q3E8	Event Queue 3 Entry Register 8
02A0 04E4	Q3E9	Event Queue 3 Entry Register 9
02A0 04E8	Q3E10	Event Queue 3 Entry Register 10
02A0 04EC	Q3E11	Event Queue 3 Entry Register 11
02A0 04F0	Q3E12	Event Queue 3 Entry Register 12
02A0 04F4	Q3E13	Event Queue 3 Entry Register 13
02A0 04F8	Q3E14	Event Queue 3 Entry Register 14
02A0 04FC	Q3E15	Event Queue 3 Entry Register 15
02A0 0500	Q4E0	Event Queue 4 Entry Register 0
02A0 0504	Q4E1	Event Queue 4 Entry Register 1
02A0 0508	Q4E2	Event Queue 4 Entry Register 2
02A0 050C	Q4E3	Event Queue 4 Entry Register 3
02A0 0510	Q4E4	Event Queue 4 Entry Register 4
02A0 0514	Q4E5	Event Queue 4 Entry Register 5
02A0 0518	Q4E6	Event Queue 4 Entry Register 6
02A0 051C	Q4E7	Event Queue 4 Entry Register 7
02A0 0520	Q4E8	Event Queue 4 Entry Register 8
02A0 0524	Q4E9	Event Queue 4 Entry Register 9
02A0 0528	Q4E10	Event Queue 4 Entry Register 10
02A0 052C	Q4E11	Event Queue 4 Entry Register 11
02A0 0530	Q4E12	Event Queue 4 Entry Register 12
02A0 0534	Q4E13	Event Queue 4 Entry Register 13
02A0 0538	Q4E14	Event Queue 4 Entry Register 14
02A0 053C	Q4E15	Event Queue 4 Entry Register 15
02A0 0540 - 02A0 05FC	-	Reserved
02A0 0600	QSTAT0	Queue Status Register 0
02A0 0604	QSTAT1	Queue Status Register 1
02A0 0608	QSTAT2	Queue Status Register 2
02A0 060C	QSTAT3	Queue Status Register 3
02A0 0610	QSTAT4	Queue Status Register 4
02A0 0614	QSTAT5	Queue Status Register 5
02A0 0618 - 02A0 061C	-	Reserved
02A0 0620	QWMTHRA	Queue Watermark Threshold A Register
02A0 0624	QWMTHRB	Queue Watermark Threshold B Register
02A0 0628 - 02A0 063C	-	Reserved
02A0 0640	CCSTAT	EDMA3CC Status Register
02A0 0644 - 02A0 06FC	-	Reserved
02A0 0700 - 02A0 07FC	-	Reserved
02A0 0800	MPFAR	Memory Protection Fault Address Register
02A0 0804	MPFSR	Memory Protection Fault Status Register
02A0 0808	MPFCR	Memory Protection Fault Command Register
02A0 080C	MPPAG	Memory Protection Page Attribute Register G
02A0 0810	MPPA0	Memory Protection Page Attribute Register 0
02A0 0814	MPPA1	Memory Protection Page Attribute Register 1
02A0 0818	MPPA2	Memory Protection Page Attribute Register 2
02A0 081C	MPPA3	Memory Protection Page Attribute Register 3
02A0 0820	MPPA4	Memory Protection Page Attribute Register 4
02A0 0824	MPPA5	Memory Protection Page Attribute Register 5
02A0 0828	MPPA6	Memory Protection Page Attribute Register 6
02A0 082C	MPPA7	Memory Protection Page Attribute Register 7
02A0 082C - 02A0 0FFC	-	Reserved
02A0 1000	ER	Event Register
02A0 1004	ERH	Event Register High
02A0 1008	ECR	Event Clear Register
02A0 100C	ECRH	Event Clear Register High
02A0 1010	ESR	Event Set Register
02A0 1014	ESRH	Event Set Register High
02A0 1018	CER	Chained Event Register
02A0 101C	CERH	Chained Event Register High
02A0 1020	EER	Event Enable Register
02A0 1024	EERH	Event Enable Register High
02A0 1028	EECR	Event Enable Clear Register
02A0 102C	EECRH	Event Enable Clear Register High
02A0 1030	EESR	Event Enable Set Register
02A0 1034	EESRH	Event Enable Set Register High
02A0 1038	SER	Secondary Event Register
02A0 103C	SERH	Secondary Event Register High
02A0 1040	SECR	Secondary Event Clear Register
02A0 1044	SECRH	Secondary Event Clear Register High
02A0 1048 - 02A0 104C	-	Reserved
02A0 1050	IER	Interrupt Enable Register
02A0 1054	IERH	Interrupt Enable High Register
02A0 1058	IECR	Interrupt Enable Clear Register
02A0 105C	IECRH	Interrupt Enable Clear High Register
02A0 1060	IESR	Interrupt Enable Set Register
02A0 1064	IESRH	Interrupt Enable Set High Register
02A0 1068	IPR	Interrupt Pending Register
02A0 106C	IPRH	Interrupt Pending High Register
02A0 1070	ICR	Interrupt Clear Register
02A0 1074	ICRH	Interrupt Clear High Register
02A0 1078	IEVAL	Interrupt Evaluate Register
02A0 107C	-	Reserved
02A0 1080	QER	QDMA Event Register
02A0 1084	QEER	QDMA Event Enable Register
02A0 1088	QEECR	QDMA Event Enable Clear Register
02A0 108C	QEESR	QDMA Event Enable Set Register
02A0 1090	QSER	QDMA Secondary Event Register
02A0 1094	QSECR	QDMA Secondary Event Clear Register
02A0 1098 - 02A0 1FFF	-	Reserved
Shadow Region 0 Channel Registers
02A0 2000	ER	Event Register
02A0 2004	ERH	Event Register High
02A0 2008	ECR	Event Clear Register
02A0 200C	ECRH	Event Clear Register High
02A0 2010	ESR	Event Set Register
02A0 2014	ESRH	Event Set Register High
02A0 2018	CER	Chained Event Register
02A0 201C	CERH	Chained Event Register High
02A0 2020	EER	Event Enable Register
02A0 2024	EERH	Event Enable Register High
02A0 2028	EECR	Event Enable Clear Register
02A0 202C	EECRH	Event Enable Clear Register High
02A0 2030	EESR	Event Enable Set Register
02A0 2034	EESRH	Event Enable Set Register High
02A0 2038	SER	Secondary Event Register
02A0 203C	SERH	Secondary Event Register High
02A0 2040	SECR	Secondary Event Clear Register
02A0 2044	SECRH	Secondary Event Clear Register High
02A0 2048 - 02A0 204C	-	Reserved
02A0 2050	IER	Interrupt Enable Register
02A0 2054	IERH	Interrupt Enable Register High
02A0 2058	IECR	Interrupt Enable Clear Register
02A0 205C	IECRH	Interrupt Enable Clear Register High
02A0 2060	IESR	Interrupt Enable Set Register
02A0 2064	IESRH	Interrupt Enable Set Register High
02A0 2068	IPR	Interrupt Pending Register
02A0 206C	IPRH	Interrupt Pending Register High
02A0 2070	ICR	Interrupt Clear Register
02A0 2074	ICRH	Interrupt Clear Register High
02A0 2078	IEVAL	Interrupt Evaluate Register
02A0 207C	-	Reserved
02A0 2080	QER	QDMA Event Register
02A0 2084	QEER	QDMA Event Enable Register
02A0 2088	QEECR	QDMA Event Enable Clear Register
02A0 208C	QEESR	QDMA Event Enable Set Register
02A0 2090	QSER	QDMA Secondary Event Register
02A0 2094	QSECR	QDMA Secondary Event Clear Register
02A0 2098 - 02A0 21FF	-	Reserved
Shadow Region 1 Channel Registers
02A0 2200	ER	Event Register
02A0 2204	ERH	Event Register High
02A0 2208	ECR	Event Clear Register
02A0 220C	ECRH	Event Clear Register High
02A0 2210	ESR	Event Set Register
02A0 2214	ESRH	Event Set Register High
02A0 2218	CER	Chained Event Register
02A0 221C	CERH	Event Enable Register
02A0 2220	EER	Event Enable Register High
02A0 2224	EERH	Event Enable Clear Register
02A0 2228	EECR	Event Enable Clear Register High
02A0 222C	EECRH	Event Enable Set Register
02A0 2230	EESR	Event Enable Set Register High
02A0 2234	EESRH	Secondary Event Register
02A0 2238	SER	Secondary Event Register High
02A0 223C	SERH	Secondary Event Clear Register
02A0 2240	SECR	Secondary Event Clear Register High
02A0 2244	SECRH	Reserved
02A0 2248 - 02A0 224C	-	Interrupt Enable Register
02A0 2250	IER	Interrupt Enable Register High
02A0 2254	IERH	Interrupt Enable Clear Register
02A0 2258	IECR	Interrupt Enable Clear Register High
02A0 225C	IECRH	Interrupt Enable Set Register
02A0 2260	IESR	Interrupt Enable Set Register High
02A0 2264	IESRH	Interrupt Pending Register
02A0 2268	IPR	Interrupt Pending Register High
02A0 226C	IPRH	Interrupt Clear Register
02A0 2270	ICR	Interrupt Clear Register High
02A0 2274	ICRH	Interrupt Evaluate Register
02A0 2278	IEVAL	Reserved
02A0 227C	-	QDMA Event Register
02A0 2280	QER
02A0 2284	QEER	QDMA Event Enable Register
02A0 2288	QEECR	QDMA Event Enable Clear Register
02A0 228C	QEESR	QDMA Event Enable Set Register
02A0 2290	QSER	QDMA Secondary Event Register
02A0 2294	QSECR	QDMA Secondary Event Clear Register
02A0 2298 - 02A0 23FF	-	Reserved
Shadow Region 2 Channel Registers
02A0 2400	ER	Event Register
02A0 2404	ERH	Event Register High
02A0 2408	ECR	Event Clear Register
02A0 240C	ECRH	Event Clear Register High
02A0 2410	ESR	Event Set Register
02A0 2414	ESRH	Event Set Register High
02A0 2418	CER	Chained Event Register
02A0 241C	CERH	Chained Event Register High
02A0 2420	EER	Event Enable Register
02A0 2424	EERH	Event Enable Register High
02A0 2428	EECR	Event Enable Clear Register
02A0 242C	EECRH	Event Enable Clear Register High
02A0 2430	EESR	Event Enable Set Register
02A0 2434	EESRH	Event Enable Set Register High
02A0 2438	SER	Secondary Event Register
02A0 243C	SERH	Secondary Event Register High
02A0 2440	SECR	Secondary Event Clear Register
02A0 2444	SECRH	Secondary Event Clear Register High
02A0 2448 - 02A0 244C	-	Reserved
02A0 2450	IER	Interrupt Enable Register
02A0 2454	IERH	Interrupt Enable Register High
02A0 2458	IECR	Interrupt Enable Clear Register
02A0 245C	IECRH	Interrupt Enable Clear Register High
02A0 2460	IESR	Interrupt Enable Set Register
02A0 2464	IESRH	Interrupt Enable Set Register High
02A0 2468	IPR	Interrupt Pending Register
02A0 246C	IPRH	Interrupt Pending Register High
02A0 2470	ICR	Interrupt Clear Register
02A0 2474	ICRH	Interrupt Clear Register High
02A0 2478	IEVAL	Interrupt Evaluate Register
02A0 247C	-	Reserved
02A0 2480	QER	QDMA Event Register
02A0 2484	QEER	QDMA Event Enable Register
02A0 2488	QEECR	QDMA Event Enable Clear Register
02A0 248C	QEESR	QDMA Event Enable Set Register
02A0 2490	QSER	QDMA Secondary Event Register
02A0 2494	QSECR	QDMA Secondary Event Clear Register
02A0 2498 - 02A0 25FF	-	Reserved
Shadow Region 3 Channel Registers
02A0 2600	ER	Event Register
02A0 2604	ERH	Event Register High
02A0 2608	ECR	Event Clear Register
02A0 260C	ECRH	Event Clear Register High
02A0 2610	ESR	Event Set Register
02A0 2614	ESRH	Event Set Register High
02A0 2618	CER	Chained Event Register
02A0 261C	CERH	Chained Event Register High
02A0 2620	EER	Event Enable Register
02A0 2624	EERH	Event Enable Register High
02A0 2628	EECR	Event Enable Clear Register
02A0 262C	EECRH	Event Enable Clear Register High
02A0 2630	EESR	Event Enable Set Register
02A0 2634	EESRH	Event Enable Set Register High
02A0 2638	SER	Secondary Event Register
02A0 263C	SERH	Secondary Event Register High
02A0 2640	SECR	Secondary Event Clear Register
02A0 2644	SECRH	Secondary Event Clear Register High
02A0 2648 - 02A0 264C	-	Reserved
02A0 2650	IER	Interrupt Enable Register
02A0 2654	IERH	Interrupt Enable Register High
02A0 2658	IECR	Interrupt Enable Clear Register
02A0 265C	IECRH	Interrupt Enable Clear Register High
02A0 2660	IESR	Interrupt Enable Set Register
02A0 2664	IESRH	Interrupt Enable Set Register High
02A0 2668	IPR	Interrupt Pending Register
02A0 266C	IPRH	Interrupt Pending Register High
02A0 2670	ICR	Interrupt Clear Register
02A0 2674	ICRH	Interrupt Clear Register High
02A0 2678	IEVAL	Interrupt Evaluate Register
02A0 267C	-	Reserved
02A0 2680	QER	QDMA Event Register
02A0 2684	QEER	QDMA Event Enable Register
02A0 2688	QEECR	QDMA Event Enable Clear Register
02A0 268C	QEESR	QDMA Event Enable Set Register
02A0 2690	QSER	QDMA Secondary Event Register
02A0 2694	QSECR	QDMA Secondary Event Clear Register
02A0 2698 - 02A0 27FF	-	Reserved
Shadow Region 4 Channel Registers
02A0 2800	ER	Event Register
02A0 2804	ERH	Event Register High
02A0 2808	ECR	Event Clear Register
02A0 280C	ECRH	Event Clear Register High
02A0 2810	ESR	Event Set Register
02A0 2814	ESRH	Event Set Register High
02A0 2818	CER	Chained Event Register
02A0 281C	CERH	Chained Event Register High
02A0 2820	EER	Event Enable Register
02A0 2824	EERH	Event Enable Register High
02A0 2828	EECR	Event Enable Clear Register
02A0 282C	EECRH	Event Enable Clear Register High
02A0 2830	EESR	Event Enable Set Register
02A0 2834	EESRH	Event Enable Set Register High
02A0 2838	SER	Secondary Event Register
02A0 283C	SERH	Secondary Event Register High
02A0 2840	SECR	Secondary Event Clear Register
02A0 2844	SECRH	Secondary Event Clear Register High
02A0 2848 - 02A0 284C	-	Reserved
02A0 2850	IER	Interrupt Enable Register
02A0 2854	IERH	Interrupt Enable Register High
02A0 2858	IECR	Interrupt Enable Clear Register
02A0 285C	IECRH	Interrupt Enable Clear Register High
02A0 2860	IESR	Interrupt Enable Set Register
02A0 2864	IESRH	Interrupt Enable Set Register High
02A0 2868	IPR	Interrupt Pending Register
02A0 286C	IPRH	Interrupt Pending Register High
02A0 2870	ICR	Interrupt Clear Register
02A0 2874	ICRH	Interrupt Clear Register High
02A0 2878	IEVAL	Interrupt Evaluate Register
02A0 287C	-	Reserved
02A0 2880	QER	QDMA Event Register
02A0 2884	QEER	QDMA Event Enable Register
02A0 2888	QEECR	QDMA Event Enable Clear Register
02A0 288C	QEESR	QDMA Event Enable Set Register
02A0 2890	QSER	QDMA Secondary Event Register
02A0 2894	QSECR	QDMA Secondary Event Clear Register
02A0 2898 - 02A0 29FF	-	Reserved
Shadow Region 5 Channel Registers
02A0 2A00	ER	Event Register
02A0 2A04	ERH	Event Register High
02A0 2A08	ECR	Event Clear Register
02A0 2A0C	ECRH	Event Clear Register High
02A0 2A10	ESR	Event Set Register
02A0 2A14	ESRH	Event Set Register High
02A0 2A18	CER	Chained Event Register
02A0 2A1C	CERH	Chained Event Register High
02A0 2A20	EER	Event Enable Register
02A0 2A24	EERH	Event Enable Register High
02A0 2A28	EECR	Event Enable Clear Register
02A0 2A2C	EECRH	Event Enable Clear Register High
02A0 2A30	EESR	Event Enable Set Register
02A0 2A34	EESRH	Event Enable Set Register High
02A0 2A38	SER	Secondary Event Register
02A0 2A3C	SERH	Secondary Event Register High
02A0 2A40	SECR	Secondary Event Clear Register
02A0 2A44	SECRH	Secondary Event Clear Register High
02A0 2A48 - 02A0 2A4C	-	Reserved
02A0 2A50	IER	Interrupt Enable Register
02A0 2A54	IERH	Interrupt Enable Register High
02A0 2A58	IECR	Interrupt Enable Clear Register
02A0 2A5C	IECRH	Interrupt Enable Clear Register High
02A0 2A60	IESR	Interrupt Enable Set Register
02A0 2A64	IESRH	Interrupt Enable Set Register High
02A0 2A68	IPR	Interrupt Pending Register
02A0 2A6C	IPRH	Interrupt Pending Register High
02A0 2A70	ICR	Interrupt Clear Register
02A0 2A74	ICRH	Interrupt Clear Register High
02A0 2A78	IEVAL	Interrupt Evaluate Register
02A0 2A7C	-	Reserved
02A0 2A80	QER	QDMA Event Register
02A0 2A84	QEER	QDMA Event Enable Register
02A0 2A88	QEECR	QDMA Event Enable Clear Register
02A0 2A8C	QEESR	QDMA Event Enable Set Register
02A0 2A90	QSER	QDMA Secondary Event Register
02A0 2A94	QSECR	QDMA Secondary Event Clear Register
02A0 2A98 - 02A0 2BFF	-	Reserved
Shadow Region 6 Channel Registers
02A0 2C00	ER	Event Register
02A0 2C04	ERH	Event Register High
02A0 2C08	ECR	Event Clear Register
02A0 2C0C	ECRH	Event Clear Register High
02A0 2C10	ESR	Event Set Register
02A0 2C14	ESRH	Event Set Register High
02A0 2C18	CER	Chained Event Register
02A0 2C1C	CERH	Chained Event Register High
02A0 2C20	EER	Event Enable Register
02A0 2C24	EERH	Event Enable Register High
02A0 2C28	EECR	Event Enable Clear Register
02A0 2C2C	EECRH	Event Enable Clear Register High
02A0 2C30	EESR	Event Enable Set Register
02A0 2C34	EESRH	Event Enable Set Register High
02A0 2C38	SER	Secondary Event Register
02A0 2C3C	SERH	Secondary Event Register High
02A0 2C40	SECR	Secondary Event Clear Register
02A0 2C44	SECRH	Secondary Event Clear Register High
02A0 2C48 - 02A0 2C4C	-	Reserved
02A0 2C50	IER	Interrupt Enable Register
02A0 2C54	IERH	Interrupt Enable Register High
02A0 2C58	IECR	Interrupt Enable Clear Register
02A0 2C5C	IECRH	Interrupt Enable Clear Register High
02A0 2C60	IESR	Interrupt Enable Set Register
02A0 2C64	IESRH	Interrupt Enable Set Register High
02A0 2C68	IPR	Interrupt Pending Register
02A0 2C6C	IPRH	Interrupt Pending Register High
02A0 2C70	ICR	Interrupt Clear Register
02A0 2C74	ICRH	Interrupt Clear Register High
02A0 2C78	IEVAL	Interrupt Evaluate Register
02A0 2C7C	-	Reserved
02A0 2C80	QER	QDMA Event Register
02A0 2C84	QEER	QDMA Event Enable Register
02A0 2C88	QEECR	QDMA Event Enable Clear Register
02A0 2C8C	QEESR	QDMA Event Enable Set Register
02A0 2C90	QSER	QDMA Secondary Event Register
02A0 2C94	QSECR	QDMA Secondary Event Clear Register
02A0 2C98 - 02A0 2DFF	-	Reserved
Shadow Region 7 Channel Registers
02A0 2E00	ER	Event Register
02A0 2E04	ERH	Event Register High
02A0 2E08	ECR	Event Clear Register
02A0 2E0C	ECRH	Event Clear Register High
02A0 2E10	ESR	Event Set Register
02A0 2E14	ESRH	Event Set Register High
02A0 2E18	CER	Chained Event Register
02A0 2E1C	CERH	Chained Event Register High
02A0 2E20	EER	Event Enable Register
02A0 2E24	EERH	Event Enable Register High
02A0 2E28	EECR	Event Enable Clear Register
02A0 2E2C	EECRH	Event Enable Clear Register High
02A0 2E30	EESR	Event Enable Set Register
02A0 2E34	EESRH	Event Enable Set Register High
02A0 2E38	SER	Secondary Event Register
02A0 2E3C	SERH	Secondary Event Register High
02A0 2E40	SECR	Secondary Event Clear Register
02A0 2E44	SECRH	Secondary Event Clear Register High
02A0 2E48 - 02A0 2E4C	-	Reserved
02A0 2E50	IER	Interrupt Enable Register
02A0 2E54	IERH	Interrupt Enable Register High
02A0 2E58	IECR	Interrupt Enable Clear Register
02A0 2E5C	IECRH	Interrupt Enable Clear Register High
02A0 2E60	IESR	Interrupt Enable Set Register
02A0 2E64	IESRH	Interrupt Enable Set Register High
02A0 2E68	IPR	Interrupt Pending Register
02A0 2E6C	IPRH	Interrupt Pending Register High
02A0 2E70	ICR	Interrupt Clear Register
02A0 2E74	ICRH	Interrupt Clear Register High
02A0 2E78	IEVAL	Interrupt Evaluate Register
02A0 2E7C	-	Reserved
02A0 2E80	QER	QDMA Event Register
02A0 2E84	QEER	QDMA Event Enable Register
02A0 2E88	QEECR	QDMA Event Enable Clear Register
02A0 2E8C	QEESR	QDMA Event Enable Set Register
02A0 2E90	QSER	QDMA Secondary Event Register
02A0 2E94	QSECR	QDMA Secondary Event Clear Register
02A0 2E98 - 02A0 2FFF	-	Reserved

Table 4-9 EDMA3 Parameter RAM

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A0 4000 - 02A0 401F	-	Parameter Set 0
02A0 4020 - 02A0 403F	-	Parameter Set 1
02A0 4040 - 02A0 405F	-	Parameter Set 2
02A0 4060 - 02A0 407F	-	Parameter Set 3
02A0 4080 - 02A0 409F	-	Parameter Set 4
02A0 40A0 - 02A0 40BF	-	Parameter Set 5
02A0 40C0 - 02A0 40DF	-	Parameter Set 6
02A0 40E0 - 02A0 40FF	-	Parameter Set 7
02A0 4100 - 02A0 411F	-	Parameter Set 8
02A0 4120 - 02A0 413F	-	Parameter Set 9
...		...
02A0 47E0 - 02A0 47FF	-	Parameter Set 63
02A0 4800 - 02A0 481F	-	Parameter Set 64
02A0 4820 - 02A0 483F	-	Parameter Set 65
...		...
02A0 5FC0 - 02A0 5FDF	-	Parameter Set 254
02A0 5FE0 - 02A0 5FFF	-	Parameter Set 255

Table 4-10 EDMA3 Transfer Controller 0 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A2 0000	PID	Peripheral Identification Register
02A2 0004	TCCFG	EDMA3TC Configuration Register
02A2 0008 - 02A2 00FC	-	Reserved
02A2 0100	TCSTAT	EDMA3TC Channel Status Register
02A2 0104 - 02A2 011C	-	Reserved
02A2 0120	ERRSTAT	Error Register
02A2 0124	ERREN	Error Enable Register
02A2 0128	ERRCLR	Error Clear Register
02A2 012C	ERRDET	Error Details Register
02A2 0130	ERRCMD	Error Interrupt Command Register
02A2 0134 - 02A2 013C	-	Reserved
02A2 0140	RDRATE	Read Rate Register
02A2 0144 - 02A2 023C	-	Reserved
02A2 0240	SAOPT	Source Active Options Register
02A2 0244	SASRC	Source Active Source Address Register
02A2 0248	SACNT	Source Active Count Register
02A2 024C	SADST	Source Active Destination Address Register
02A2 0250	SABIDX	Source Active Source B-Index Register
02A2 0254	SAMPPRXY	Source Active Memory Protection Proxy Register
02A2 0258	SACNTRLD	Source Active Count Reload Register
02A2 025C	SASRCBREF	Source Active Source Address B-Reference Register
02A2 0260	SADSTBREF	Source Active Destination Address B-Reference Register
02A2 0264 - 02A2 027C	-	Reserved
02A2 0280	DFCNTRLD	Destination FIFO Set Count Reload
02A2 0284	DFSRCBREF	Destination FIFO Set Destination Address B Reference Register
02A2 0288	DFDSTBREF	Destination FIFO Set Destination Address B Reference Register
02A2 028C - 02A2 02FC	-	Reserved
02A2 0300	DFOPT0	Destination FIFO Options Register 0
02A2 0304	DFSRC0	Destination FIFO Source Address Register 0
02A2 0308	DFCNT0	Destination FIFO Count Register 0
02A2 030C	DFDST0	Destination FIFO Destination Address Register 0
02A2 0310	DFBIDX0	Destination FIFO BIDX Register 0
02A2 0314	DFMPPRXY0	Destination FIFO Memory Protection Proxy Register 0
02A2 0318 - 02A2 033C	-	Reserved
02A2 0340	DFOPT1	Destination FIFO Options Register 1
02A2 0344	DFSRC1	Destination FIFO Source Address Register 1
02A2 0348	DFCNT1	Destination FIFO Count Register 1
02A2 034C	DFDST1	Destination FIFO Destination Address Register 1
02A2 0350	DFBIDX1	Destination FIFO BIDX Register 1
02A2 0354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
02A2 0358 - 02A2 037C	-	Reserved
02A2 0380	DFOPT2	Destination FIFO Options Register 2
02A2 0384	DFSRC2	Destination FIFO Source Address Register 2
02A2 0388	DFCNT2	Destination FIFO Count Register 2
02A2 038C	DFDST2	Destination FIFO Destination Address Register 2
02A2 0390	DFBIDX2	Destination FIFO BIDX Register 2
02A2 0394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
02A2 0398 - 02A2 03BC	-	Reserved
02A2 03C0	DFOPT3	Destination FIFO Options Register 3
02A2 03C4	DFSRC3	Destination FIFO Source Address Register 3
02A2 03C8	DFCNT3	Destination FIFO Count Register 3
02A2 03CC	DFDST3	Destination FIFO Destination Address Register 3
02A2 03D0	DFBIDX3	Destination FIFO BIDX Register 3
02A2 03D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3
02A2 03D8 - 02A2 7FFC	-	Reserved

Table 4-11 EDMA3 Transfer Controller 1 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A2 8000	PID	Peripheral Identification Register
02A2 8004	TCCFG	EDMA3TC Configuration Register
02A2 8008 - 02A2 80FC	-	Reserved
02A2 8100	TCSTAT	EDMA3TC Channel Status Register
02A2 8104 - 02A2 811C	-	Reserved
02A2 8120	ERRSTAT	Error Register
02A2 8124	ERREN	Error Enable Register
02A2 8128	ERRCLR	Error Clear Register
02A2 812C	ERRDET	Error Details Register
02A2 8130	ERRCMD	Error Interrupt Command Register
02A2 8134 - 02A2 813C	-	Reserved
02A2 8140	RDRATE	Read Rate Register
02A2 8144 - 02A2 823C	-	Reserved
02A2 8240	SAOPT	Source Active Options Register
02A2 8244	SASRC	Source Active Source Address Register
02A2 8248	SACNT	Source Active Count Register
02A2 824C	SADST	Source Active Destination Address Register
02A2 8250	SABIDX	Source Active Source B-Index Register
02A2 8254	SAMPPRXY	Source Active Memory Protection Proxy Register
02A2 8258	SACNTRLD	Source Active Count Reload Register
02A2 825C	SASRCBREF	Source Active Source Address B-Reference Register
02A2 8260	SADSTBREF	Source Active Destination Address B-Reference Register
02A2 8264 - 02A2 827C	-	Reserved
02A2 8280	DFCNTRLD	Destination FIFO Set Count Reload
02A2 8284	DFSRCBREF	Destination FIFO Set Destination Address B Reference Register
02A2 8288	DFDSTBREF	Destination FIFO Set Destination Address B Reference Register
02A2 828C - 02A2 82FC	-	Reserved
02A2 8300	DFOPT0	Destination FIFO Options Register 0
02A2 8304	DFSRC0	Destination FIFO Source Address Register 0
02A2 8308	DFCNT0	Destination FIFO Count Register 0
02A2 830C	DFDST0	Destination FIFO Destination Address Register 0
02A2 8310	DFBIDX0	Destination FIFO BIDX Register 0
02A2 8314	DFM PPRXY0	Destination FIFO Memory Protection Proxy Register 0
02A2 8318 - 02A2 833C	-	Reserved
02A2 8340	DFOPT1	Destination FIFO Options Register 1
02A2 8344	DFSRC1	Destination FIFO Source Address Register 1
02A2 8348	DFCNT1	Destination FIFO Count Register 1
02A2 834C	DFDST1	Destination FIFO Destination Address Register 1
02A2 8350	DFBIDX1	Destination FIFO BIDX Register 1
02A2 8354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
02A2 8358 - 02A2 837C	-	Reserved
02A2 8380	DFOPT2	Destination FIFO Options Register 2
02A2 8384	DFSRC2	Destination FIFO Source Address Register 2
02A2 8388	DFCNT2	Destination FIFO Count Register 2
02A2 838C	DFDST2	Destination FIFO Destination Address Register 2
02A2 8390	DFBIDX2	Destination FIFO BIDX Register 2
02A2 8394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
02A2 8398 - 02A2 83BC	-	Reserved
02A2 83C0	DFOPT3	Destination FIFO Options Register 3
02A2 83C4	DFSRC3	Destination FIFO Source Address Register 3
02A2 83C8	DFCNT3	Destination FIFO Count Register 3
02A2 83CC	DFDST3	Destination FIFO Destination Address Register 3
02A2 83D0	DFBIDX3	Destination FIFO BIDX Register 3
02A2 83D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3
02A2 83D8 - 02A2 FFFC	-	Reserved

Table 4-12 EDMA3 Transfer Controller 2 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A3 0000	PID	Peripheral Identification Register
02A3 0004	TCCFG	EDMA3TC Configuration Register
02A3 0008 - 02A3 00FC	-	Reserved
02A3 0100	TCSTAT	EDMA3TC Channel Status Register
02A3 0104 - 02A3 011C	-	Reserved
02A3 0120	ERRSTAT	Error Register
02A3 0124	ERREN	Error Enable Register
02A3 0128	ERRCLR	Error Clear Register
02A3 012C	ERRDET	Error Details Register
02A3 0130	ERRCMD	Error Interrupt Command Register
02A3 0134 - 02A3 013C	-	Reserved
02A3 0140	RDRATE	Read Rate Register
02A3 0144 - 02A3 023C	-	Reserved
02A3 0240	SAOPT	Source Active Options Register
02A3 0244	SASRC	Source Active Source Address Register
02A3 0248	SACNT	Source Active Count Register
02A3 024C	SADST	Source Active Destination Address Register
02A3 0250	SABIDX	Source Active Source B-Index Register
02A3 0254	SAMPPRXY	Source Active Memory Protection Proxy Register
02A3 0258	SACNTRLD	Source Active Count Reload Register
02A3 025C	SASRCBREF	Source Active Source Address B-Reference Register
02A3 0260	SADSTBREF	Source Active Destination Address B-Reference Register
02A3 0264 - 02A3 027C	-	Reserved
02A3 0280	DFCNTRLD	Destination FIFO Set Count Reload
02A3 0284	DFSRCBREF	Destination FIFO Set Destination Address B Reference Register
02A3 0288	DFDSTBREF	Destination FIFO Set Destination Address B Reference Register
02A3 028C - 02A3 02FC	-	Reserved
02A3 0300	DFOPT0	Destination FIFO Options Register 0
02A3 0304	DFSRC0	Destination FIFO Source Address Register 0
02A3 0308	DFCNT0	Destination FIFO Count Register 0
02A3 030C	DFDST0	Destination FIFO Destination Address Register 0
02A3 0310	DFBIDX0	Destination FIFO BIDX Register 0
02A3 0314	DFMPPRXY0	Destination FIFO Memory Protection Proxy Register 0
02A3 0318 - 02A3 033C	-	Reserved
02A3 0340	DFOPT1	Destination FIFO Options Register 1
02A3 0344	DFSRC1	Destination FIFO Source Address Register 1
02A3 0348	DFCNT1	Destination FIFO Count Register 1
02A3 034C	DFDST1	Destination FIFO Destination Address Register 1
02A3 0350	DFBIDX1	Destination FIFO BIDX Register 1
02A3 0354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
02A3 0358 - 02A3 037C	-	Reserved
02A3 0380	DFOPT2	Destination FIFO Options Register 2
02A3 0384	DFSRC2	Destination FIFO Source Address Register 2
02A3 0388	DFCNT2	Destination FIFO Count Register 2
02A3 038C	DFDST2	Destination FIFO Destination Address Register 2
02A3 0390	DFBIDX2	Destination FIFO BIDX Register 2
02A3 0394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
02A3 0398 - 02A3 03BC	-	Reserved
02A3 03C0	DFOPT3	Destination FIFO Options Register 3
02A3 03C4	DFSRC3	Destination FIFO Source Address Register 3
02A3 03C8	DFCNT3	Destination FIFO Count Register 3
02A3 03CC	DFDST3	Destination FIFO Destination Address Register 3
02A3 03D0	DFBIDX3	Destination FIFO BIDX Register 3
02A3 03D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3
02A3 03D8 - 02A3 7FFC	-	Reserved

Table 4-13 EDMA3 Transfer Controller 3 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A3 8000	PID	Peripheral Identification Register
02A3 8004	TCCFG	EDMA3TC Configuration Register
02A3 8008 - 02A3 80FC	-	Reserved
02A3 8100	TCSTAT	EDMA3TC Channel Status Register
02A3 8104 - 02A3 811C	-	Reserved
02A3 8120	ERRSTAT	Error Register
02A3 8124	ERREN	Error Enable Register
02A3 8128	ERRCLR	Error Clear Register
02A3 812C	ERRDET	Error Details Register
02A3 8130	ERRCMD	Error Interrupt Command Register
02A3 8134 - 02A3 813C	-	Reserved
02A3 8140	RDRATE	Read Rate Register
02A3 8144 - 02A3 823C	-	Reserved
02A3 8240	SAOPT	Source Active Options Register
02A3 8244	SASRC	Source Active Source Address Register
02A3 8248	SACNT	Source Active Count Register
02A3 824C	SADST	Source Active Destination Address Register
02A3 8250	SABIDX	Source Active Source B-Index Register
02A3 8254	SAMPPRXY	Source Active Memory Protection Proxy Register
02A3 8258	SACNTRLD	Source Active Count Reload Register
02A3 825C	SASRCBREF	Source Active Source Address B-Reference Register
02A3 8260	SADSTBREF	Source Active Destination Address B-Reference Register
02A3 8264 - 02A3 827C	-	Reserved
02A3 8280	DFCNTRLD	Destination FIFO Set Count Reload
02A3 8284	DFSRCBREF	Destination FIFO Set Destination Address B Reference Register
02A3 8288	DFDSTBREF	Destination FIFO Set Destination Address B Reference Register
02A3 828C - 02A3 82FC	-	Reserved
02A3 8300	DFOPT0	Destination FIFO Options Register 0
02A3 8304	DFSRC0	Destination FIFO Source Address Register 0
02A3 8308	DFCNT0	Destination FIFO Count Register 0
02A3 830C	DFDST0	Destination FIFO Destination Address Register 0
02A3 8310	DFBIDX0	Destination FIFO BIDX Register 0
02A3 8314	DFMPPRXY0	Destination FIFO Memory Protection Proxy Register 0
02A3 8318 - 02A3 833C	-	Reserved
02A3 8340	DFOPT1	Destination FIFO Options Register 1
02A3 8344	DFSRC1	Destination FIFO Source Address Register 1
02A3 8348	DFCNT1	Destination FIFO Count Register 1
02A3 834C	DFDST1	Destination FIFO Destination Address Register 1
02A3 8350	DFBIDX1	Destination FIFO BIDX Register 1
02A3 8354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
02A3 8358 - 02A3 837C	-	Reserved
02A3 8380	DFOPT2	Destination FIFO Options Register 2
02A3 8384	DFSRC2	Destination FIFO Source Address Register 2
02A3 8388	DFCNT2	Destination FIFO Count Register 2
02A3 838C	DFDST2	Destination FIFO Destination Address Register 2
02A3 8390	DFBIDX2	Destination FIFO BIDX Register 2
02A3 8394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
02A3 8398 - 02A3 83BC	-	Reserved
02A3 83C0	DFOPT3	Destination FIFO Options Register 3
02A3 83C4	DFSRC3	Destination FIFO Source Address Register 3
02A3 83C8	DFCNT3	Destination FIFO Count Register 3
02A3 83CC	DFDST3	Destination FIFO Destination Address Register 3
02A3 83D0	DFBIDX3	Destination FIFO BIDX Register 3
02A3 83D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3
02A3 83D8 - 02A3 FFFC	-	Reserved

Table 4-14 EDMA3 Transfer Controller 4 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A4 0000	PID	Peripheral Identification Register
02A4 0004	TCCFG	EDMA3TC Configuration Register
02A4 0008 - 02A4 00FC	-	Reserved
02A4 0100	TCSTAT	EDMA3TC Channel Status Register
02A4 0104 - 02A4 011C	-	Reserved
02A4 0120	ERRSTAT	Error Register
02A4 0124	ERREN	Error Enable Register
02A4 0128	ERRCLR	Error Clear Register
02A4 012C	ERRDET	Error Details Register
02A4 0130	ERRCMD	Error Interrupt Command Register
02A4 0134 - 02A4 013C	-	Reserved
02A4 0140	RDRATE	Read Rate Register
02A4 0144 - 02A4 023C	-	Reserved
02A4 0240	SAOPT	Source Active Options Register
02A4 0244	SASRC	Source Active Source Address Register
02A4 0248	SACNT	Source Active Count Register
02A4 024C	SADST	Source Active Destination Address Register
02A4 0250	SABIDX	Source Active Source B-Index Register
02A4 0254	SAMPPRXY	Source Active Memory Protection Proxy Register
02A4 0258	SACNTRLD	Source Active Count Reload Register
02A4 025C	SASRCBREF	Source Active Source Address B-Reference Register
02A4 0260	SADSTBREF	Source Active Destination Address B-Reference Register
02A4 0264 - 02A4 027C	-	Reserved
02A4 0280	DFCNTRLD	Destination FIFO Set Count Reload
02A4 0284	DFSRCBREF	Destination FIFO Set Destination Address B Reference Register
02A4 0288	DFDSTBREF	Destination FIFO Set Destination Address B Reference Register
02A4 028C - 02A4 02FC	-	Reserved
02A4 0300	DFOPT0	Destination FIFO Options Register 0
02A4 0304	DFSRC0	Destination FIFO Source Address Register 0
02A4 0308	DFCNT0	Destination FIFO Count Register 0
02A4 030C	DFDST0	Destination FIFO Destination Address Register 0
02A4 0310	DFBIDX0	Destination FIFO BIDX Register 0
02A4 0314	DFMPPRXY0	Destination FIFO Memory Protection Proxy Register 0
02A4 0318 - 02A4 033C	-	Reserved
02A4 0340	DFOPT1	Destination FIFO Options Register 1
02A4 0344	DFSRC1	Destination FIFO Source Address Register 1
02A4 0348	DFCNT1	Destination FIFO Count Register 1
02A4 034C	DFDST1	Destination FIFO Destination Address Register 1
02A4 0350	DFBIDX1	Destination FIFO BIDX Register 1
02A4 0354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
02A4 0358 - 02A4 037C	-	Reserved
02A4 0380	DFOPT2	Destination FIFO Options Register 2
02A4 0384	DFSRC2	Destination FIFO Source Address Register 2
02A4 0388	DFCNT2	Destination FIFO Count Register 2
02A4 038C	DFDST2	Destination FIFO Destination Address Register 2
02A4 0390	DFBIDX2	Destination FIFO BIDX Register 2
02A4 0394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
02A4 0398 - 02A4 03BC	-	Reserved
02A4 03C0	DFOPT3	Destination FIFO Options Register 3
02A4 03C4	DFSRC3	Destination FIFO Source Address Register 3
02A4 03C8	DFCNT3	Destination FIFO Count Register 3
02A4 03CC	DFDST3	Destination FIFO Destination Address Register 3
02A4 03D0	DFBIDX3	Destination FIFO BIDX Register 3
02A4 03D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3
02A4 03D8 - 02A4 7FFC	-	Reserved

Table 4-15 EDMA3 Transfer Controller 5 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02A4 8000	PID	Peripheral Identification Register
02A4 8004	TCCFG	EDMA3TC Configuration Register
02A4 8008 - 02A4 80FC	-	Reserved
02A4 8100	TCSTAT	EDMA3TC Channel Status Register
02A4 8104 - 02A4 811C	-	Reserved
02A4 8120	ERRSTAT	Error Register
02A4 8124	ERREN	Error Enable Register
02A4 8128	ERRCLR	Error Clear Register
02A4 812C	ERRDET	Error Details Register
02A4 8130	ERRCMD	Error Interrupt Command Register
02A4 8134 - 02A4 813C	-	Reserved
02A4 8140	RDRATE	Read Rate Register
02A4 8144 - 02A4 823C	-	Reserved
02A4 8240	SAOPT	Source Active Options Register
02A4 8244	SASRC	Source Active Source Address Register
02A4 8248	SACNT	Source Active Count Register
02A4 824C	SADST	Source Active Destination Address Register
02A4 8250	SABIDX	Source Active Source B-Index Register
02A4 8254	SAMPPRXY	Source Active Memory Protection Proxy Register
02A4 8258	SACNTRLD	Source Active Count Reload Register
02A4 825C	SASRCBREF	Source Active Source Address B-Reference Register
02A4 8260	SADSTBREF	Source Active Destination Address B-Reference Register
02A4 8264 - 02A4 827C	-	Reserved
02A4 8280	DFCNTRLD	Destination FIFO Set Count Reload
02A4 8284	DFSRCBREF	Destination FIFO Set Destination Address B Reference Register
02A4 8288	DFDSTBREF	Destination FIFO Set Destination Address B Reference Register
02A4 828C - 02A4 82FC	-	Reserved
02A4 8300	DFOPT0	Destination FIFO Options Register 0
02A4 8304	DFSRC0	Destination FIFO Source Address Register 0
02A4 8308	DFCNT0	Destination FIFO Count Register 0
02A4 830C	DFDST0	Destination FIFO Destination Address Register 0
02A4 8310	DFBIDX0	Destination FIFO BIDX Register 0
02A4 8314	DFMPPRXY0	Destination FIFO Memory Protection Proxy Register 0
02A4 8318 - 02A4 833C	-	Reserved
02A4 8340	DFOPT1	Destination FIFO Options Register 1
02A4 8344	DFSRC1	Destination FIFO Source Address Register 1
02A4 8348	DFCNT1	Destination FIFO Count Register 1
02A4 834C	DFDST1	Destination FIFO Destination Address Register 1
02A4 8350	DFBIDX1	Destination FIFO BIDX Register 1
02A4 8354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
02A4 8358 - 02A4 837C	-	Reserved
02A4 8380	DFOPT2	Destination FIFO Options Register 2
02A4 8384	DFSRC2	Destination FIFO Source Address Register 2
02A4 8388	DFCNT2	Destination FIFO Count Register 2
02A4 838C	DFDST2	Destination FIFO Destination Address Register 2
02A4 8390	DFBIDX2	Destination FIFO BIDX Register 2
02A4 8394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
02A4 8398 - 02A4 83BC	-	Reserved
02A4 83C0	DFOPT3	Destination FIFO Options Register 3
02A4 83C4	DFSRC3	Destination FIFO Source Address Register 3
02A4 83C8	DFCNT3	Destination FIFO Count Register 3
02A4 83CC	DFDST3	Destination FIFO Destination Address Register 3
02A4 83D0	DFBIDX3	Destination FIFO BIDX Register 3
02A4 83D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3
02A4 83D8 - 02A4 FFFC	-	Reserved

4.7.2 Interrupts

4.7.2.1 Interrupt Sources and Interrupt Controller

The CPU interrupts on the C6457 device are configured through the C64x+ Megamodule Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the megamodule) and chip-level events. Table 4-16 shows the mapping of system events. For more information on the Interrupt Controller, see the TMS320C64x+ Megamodule Reference Guide (SPRU871).

Table 4-16 C6457 System Event Mapping

EVENT NUMBER	INTERRUPT EVENT	DESCRIPTION
0⁽¹⁾	EVT0	Output of event combiner 0 in interrupt controller, for events 1 - 31.
1⁽¹⁾	EVT1	Output of event combiner 1 in interrupt controller, for events 32 - 63.
2⁽¹⁾	EVT2	Output of event combiner 2 in interrupt controller, for events 64 - 95.
3⁽¹⁾	EVT3	Output of event combiner 3 in interrupt controller, for events 96 - 127.
4 - 8	Reserved	Reserved. These system events are not connected and, therefore, not used.
9⁽¹⁾	EMU_DTDMA	EMU interrupt for: Host scan access DTDMA transfer complete AET interrupt
10	None	This system event is not connected and, therefore, not used.
11⁽¹⁾	EMU_RTDXRX	EMU real-time data exchange (RTDX) receive complete
12⁽¹⁾	EMU_RTDXTX	EMU RTDX transmit complete
13(1)	IDMA0	IDMA channel 0 interrupt
14⁽¹⁾	IDMA1	IDMA channel 1 interrupt
15	DSPINT	HPI-to-DSP interrupt
16	I2CINT	I²C interrupt
17	MACINT	Ethernet MAC interrupt
18	AEASYNCERR	EMIFA error interrupt
19	Reserved	Reserved. This system event is not connected and, therefore, not used.
20	INTDST0	RapidIO interrupt 0
21	INTDST1	RapidIO interrupt 1
22	INTDST2	RapidIO interrupt 2
23	INTDST3	RapidIO interrupt 3
24	EDMA3CC_GINT	EDMA3 channel global completion interrupt
25	MACRXINT	Ethernet MAC receive interrupt
26	MACTXINT	Ethernet MAC transmit interrupt
27	MACTHRESH	Ethernet MAC receive threshold interrupt
28	INTDST4	RapidIO interrupt 4
29	INTDST5	RapidIO interrupt 5
30	INTDST6	RapidIO interrupt 6
31	Reserved	Reserved. These system events are not connected and, therefore, not used.
32	VCP2_INT	VCP2 error interrupt
33	TCP2A_INT	TCP2_A error interrupt
34	TCP2B_INT	TCP2_B error interrupt
35	Reserved	Reserved. These system events are not connected and, therefore, not used.
36	UINT	UTOPIA interrupt
37 - 39	Reserved	Reserved. These system events are not connected and, therefore, not used.
40	RINT0	McBSP0 receive interrupt
41	XINT0	McBSP0 transmit interrupt
42	RINT1	McBSP1 receive interrupt
43	XINT1	McBSP1 transmit interrupt
44 - 50	Reserved	Reserved. Do not use.
51	GPINT0	GPIO interrupt
52	GPINT1	GPIO interrupt
53	GPINT2	GPIO interrupt
54	GPINT3	GPIO interrupt
55	GPINT4	GPIO interrupt
56	GPINT5	GPIO interrupt
57	GPINT6	GPIO interrupt
58	GPINT7	GPIO interrupt
59	GPINT8	GPIO interrupt
60	GPINT9	GPIO interrupt
61	GPINT10	GPIO interrupt
62	GPINT11	GPIO interrupt
63	GPINT12	GPIO interrupt
64	GPINT13	GPIO interrupt
65	GPINT14	GPIO interrupt
66	GPINT15	GPIO interrupt
67	TINTLO0	Timer 0 lower counter interrupt
68	TINTHI0	Timer 0 higher counter interrupt
69	TINTLO1	Timer 1 lower counter interrupt
70	TINTHI1	Timer 1 higher counter interrupt
71	EDMA3CC_INT0	EDMA3CC completion interrupt - Mask0
72	EDMA3CC_INT1	EDMA3CC completion interrupt - Mask1
73	EDMA3CC_INT2	EDMA3CC completion interrupt - Mask2
74	EDMA3CC_INT3	EDMA3CC completion interrupt - Mask3
75	EDMA3CC_INT4	EDMA3CC completion interrupt - Mask4
76	EDMA3CC_INT5	EDMA3CC completion interrupt - Mask5
77	EDMA3CC_INT6	EDMA3CC completion interrupt - Mask6
78	EDMA3CC_INT7	EDMA3CC completion interrupt - Mask7
79	EDMA3CC_ERRINT	EDMA3CC error interrupt
80	Reserved	Reserved. This system event is not connected and, therefore, not used.
81	EDMA3TC0_ERRINT	EDMA3TC0 error interrupt
82	EDMA3TC1_ERRINT	EDMA3TC1 error interrupt
83	EDMA3TC2_ERRINT	EDMA3TC2 error interrupt
84	EDMA3TC3_ERRINT	EDMA3TC3 error interrupt
85	EDMA3CC_AET	EDMA3CC AET Event
86	EDMA3TC4_ERRINT	EDMA3TC4 error interrupt
87	EDMA3TC5_ERRINT	EDMA3TC5 error interrupt
88 - 93	Reserved	Reserved. These system events are not connected and, therefore, not used.
94	ETBOVFLINT	Overflow condition occurred in ETB
95	ETBUNFLINT	Underflow condition occurred in ETB
96⁽¹⁾	INTERR	Interrupt Controller dropped CPU interrupt event
97⁽¹⁾	EMC_IDMAERR	EMC invalid IDMA parameters
98 - 99	Reserved	Reserved. These system events are not connected and, therefore, not used.
100⁽¹⁾	EFIINTA	EFI interrupt from side A
101⁽¹⁾	EFIINTB	EFI interrupt from side B
102 - 112	Reserved	Reserved. These system events are not connected and, therefore, not used.
113⁽¹⁾	L1P_ED1	L1P single bit error detected during DMA read
114 - 115	Reserved	Reserved. These system events are not connected and, therefore, not used.
116⁽¹⁾	L2_ED1	L2 single bit error detected
117⁽¹⁾	L2_ED2	L2 two bit error detected
118⁽¹⁾	PDC_INT	Powerdown sleep interrupt
119⁽¹⁾	SYS_CMPA	CPU memory protection fault
120⁽¹⁾	L1P_CMPA	L1P CPU memory protection fault
121⁽¹⁾	L1P_DMPA	L1P DMA memory protection fault
122⁽¹⁾	L1D_CMPA	L1D CPU memory protection fault
123⁽¹⁾	L1D_DMPA	L1D DMA memory protection fault
124⁽¹⁾	L2_CMPA	L2 CPU memory protection fault
125⁽¹⁾	L2_DMPA	L2 DMA memory protection fault
126⁽¹⁾	IDMA_CMPA	IDMA CPU memory protection fault
127⁽¹⁾	IDMA_BUSERR	IDMA bus error interrupt

(1) This system event is generated from within the C64x+ megamodule.

4.7.2.2 External Interrupts Electrical Data/Timing

Table 4-17 Timing Requirements for External Interrupts⁽¹⁾

(see Figure 4-11)

NO.			MIN	MAX	UNIT
1	t_w(NMIL)	Width of the NMI interrupt pulse low	6P		ns
2	t_w(NMIH)	Width of the NMI interrupt pulse high	6P		ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

SM320C6457-HIREL NMI_Interrupt_Timing_6484.gif

Figure 4-11 NMI Interrupt Timing

4.7.3 Reset Controller

The reset controller detects the different type of resets supported on the C6457 device and manages the distribution of those resets throughout the device.

The C6457 device has several types of resets:

Power-on reset
Warm reset
System reset
CPU reset

Table 4-18 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more information on the effects of each reset on the PLL controllers and their clocks, see Section 4.6.3.

Table 4-18 Reset Types

TYPE	INITIATOR	EFFECT(S)
Power-on Reset	POR pin	Resets the entire chip including the test and emulation logic. The device configuration pins are latched only during POR.
Warm Reset	RESET pin	Resets everything except for the test and emulation logic and PLL2. The emulator stays alive during warm reset. The device configuration pins are not re-latched. DDR2 memory contents will be preserved if the user places the DDR2 SDRAM in “Self-Refresh” mode before starting a Warm Reset sequence.
System Reset	Emulator Serial RapidIO PLLCTL⁽¹⁾	System reset, by default, behaves as hard reset, but can be configured as soft reset if initiated by Serial RapidIO or PLLCTL. Emulator-initiated reset is always a hard reset. Hard reset effects are the same as those of a warm reset. Soft reset means external memory contents can be maintained, it does not affect the clock logic, or the power control logic of the peripherals. See Section 4.7.3.3 for more details. A system reset does not reset the test and emulation circuitry. The device configuration pins are also not re-latched.
CPU Local Reset	Watchdog Timer	CPU local reset.

(1) All masters in the device have access to the PLLCTL registers.

4.7.3.1 Power-on Reset (POR Pin)

Power-on reset is initiated by the POR pin and is used to reset the entire device, including the test and emulation logic. Power-on reset is also referred to as a cold reset because the device usually goes through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Note that a device power-up cycle is not required to initiate a power-on reset. For power-on reset, the main PLL controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller. For the secondary PLL, the PLL is enabled and always clocking when POR is not asserted.

The following sequence must be followed during a power-on reset:

Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control registers (for more details, see Section 5.5.2).
Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.
POR must be held active until all supplies on the board are stable then for at least an additional 100 µs + 2000 CLKIN2 cycles.
The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. PLL2 is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.
After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide by settings.
The device is now out of reset and device execution begins as dictated by the selected boot mode.

NOTE

To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the POR pin.

4.7.3.2 Warm Reset (RESET Pin)

A warm reset will reset everything on the device except the PLLs, PLL controller, test, and emulation logic. POR should also remain de-asserted during this time.

The following sequence must be followed during a warm reset:

The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.
Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.
After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

NOTE

The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.

NOTE

The DDR2 SDRAM contents will also be preserved if the user places the SDRAM into Self-Refresh mode before starting a Warm Reset sequence. Please see theTMS320C6457 DSP DDR2 Memory Controller User’s Guide (SPRUGK5).

4.7.3.3 System Reset

In a System Reset, test and emulation logic are unaffected. The device configuration pins are also not re-latched. System reset can be initiated by the emulator or Serial RapidIO or by the PLLCTL:

Emulator Initiated System Reset: The emulator initiated System Reset is always a Hard Reset. The effects of a Hard Reset are the same as a Warm Reset (defined in Section 4.7.3.2).
Serial RapidIO Initiated System Reset: The Serial Rapid IO initiated System Reset can be configured by the RSTCFG register (see Section 4.7.3.6.3) as a Soft Reset or Hard Reset. For more information on the Serial RapidIO initiated system reset, see Section 4.2 of the TMS320C6457 DSP Serial RapidIO (SRIO) User's Guide (SPRUGK4).
PLLCTL Initiated System Reset: The PLLCTL module can initiate a System Reset using the RSTCTRL register; see Section 4.7.3.6.2. The PLLCTL initiated System Reset can be configured by the RSTCFG register (see Section 4.7.3.6.3) as a Soft Reset or Hard Reset.

In the case of a Soft Reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore, the enabled/disabled state of the peripherals is not affected. The following external memory contents are maintained during a soft reset:

DDR2 Memory Controller: The DDR2 Memory Controller registers are not reset. In addition, the DDR2 SDRAM memory content is retained if the user places the DDR2 SDRAM in self-refresh mode before invoking the soft reset.
EMIFA: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are not reset.

During a soft reset, the following happens:

The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate through the system. Internal system clocks are not affected. PLLs also remain locked.
After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL controllers pause their system clocks for about 10 cycles.
- At this point:
  - The state of the peripherals before the soft reset is not changed. For example, if McBSP0 was in the enabled state before soft reset, it will remain in the enabled state after soft reset.
  - The I/O pins are controlled as dictated by the DEVSTAT register.
  - The DDR2 Memory Controller and EMIFA registers retain their previous values. Only the DDR2 Memory Controller and EMIFA state machines are reset by the soft reset.
  - The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Since the configuration pins (including the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.

4.7.3.4 CPU Reset

Timer1 can provide a local CPU reset if it is set up in watchdog mode.

4.7.3.5 Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request. The reset request priorities are as follows (high to low):

Power-on reset
Warm reset and system reset

4.7.3.6 Reset Controller Register

There are three reset controller registers: Reset Type Status (RSTYPE) register (029A 00E4), Software Reset Control (RSTCTRL) register (029A 00E8), and Reset Configuration (RSTCFG) register (029A 00EC). All three registers fall in the same memory range as the PLL1 Controller registers [029A 0000 - 029A 0170] (see Table 4-24).

4.7.3.6.1 Reset Type Status Register

The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status register is shown in Figure 4-12 and described in Table 4-19.

Figure 4-12 Reset Type Status Register (RSTYPE) (Address - 029A 00E4h)

Reserved

EMU-RST

Reserved

R-0

Reserved

SRIORST

Reserved

PLLCTRLRST

WRST

POR

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-19 Reset Type Status Register (RSTYPE) Field Descriptions

Bit	Acronym	Description
31:29	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
28	EMU-RST	System reset initiated by emulator. 0 = Not the last reset to occur. 1 = The last reset to occur.
27:9	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
8	SRIORST	System reset initiated by SRIO. 0 = Not the last reset to occur. 1 = The last reset to occur.
7:3	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
2	PLLCTLRST	System reset initiated by PLLCTL. 0 = Not the last reset to occur. 1 = The last reset to occur.
1	WRST	Warm reset. 0 = Warm reset was not the last reset to occur. 1 = Warm reset was the last reset to occur.
0	POR	Power-on reset. 0 = Power-on reset was not the last reset to occur. 1 = Power-on reset was the last reset to occur.

4.7.3.6.2 Software Reset Control Register

This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control register (RSTCTRL) is shown in Figure 4-13 and described in Table 4-20.

Figure 4-13 Software Reset Control Register (RSTCTRL) (Hex Address - 029A 00E8h)

Reserved

SWRST⁽¹⁾

R-0x0000

R/W-0x

KEY

R/W-0x0003

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) Writes are conditional based on valid key.

Table 4-20 Software Reset Control Register Field Descriptions

Bit	Acronym	Description
31:17	Reserved	Reserved.
16	SWRST	Software reset 0 = Reset 1 = Not reset
15:0	KEY	Key used to enable writes to RSTCTRL and RSTCFG.

4.7.3.6.3 Reset Configuration Register

This register is used to configure the type of system resets initiated by the SRIO module or a PLL controller; i.e., a hard reset or a soft reset. By default, both the system resets will be hard resets. The Reset Configuration register (RSTCFG) is shown in Figure 4-14 and described in Table 4-21.

Figure 4-14 Reset Configuration Register (RSTCFG) (Address - 029A 00ECh)

Reserved

R-0x2000

Reserved

PLLCTLRSTTYPE

Reserved

SRIORSTTYPE

R-0x000

R/W-0⁽¹⁾

R-0x000

R/W-0x0⁽¹⁾

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) Writes are conditional based on valid key. For details, see Section 4.7.3.6.2.

Table 4-21 Reset Configuration Register (RSTCFG) Field Descriptions

Bit	Acronym	Description
31:14	Reserved	Reserved.
13	PLLCTLRSTTYPE	PLL controller initiates a software driven reset of type: 0 = Hard reset (default) 1 = Soft reset
12:1	Reserved	Reserved.
0	SRIORSTTYPE	SRIO module initiates a reset of type: 0 = Hard Reset (default) 1 = Soft Reset

4.7.4 PLL1 and PLL1 Controller

This section provides a description of the PLL1 controller. For details on the operation of the PLL controller module, see the TMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (SPRUGL3).

NOTE

The PLL1 controller registers can be accessed by any master in the device.

The main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment, and gating for the system clocks to the device. Figure 4-15 shows a block diagram of the PLL controller. The following paragraphs define the clocks and PLL controller parameters.

SM320C6457-HIREL PLL1_and_PLL1_Controller_6484.gif

Figure 4-15 PLL1 and PLL1 Controller

The inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output. The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

PLL1 power is supplied externally via the PLL1 power-supply pin (PLLV1). An external EMI filter circuit must be added to PLLV1, as shown in Figure 4-15. The 1.8-V supply of the EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DV_DD18. TI requires EMI filter manufacturer Murata, part number NFM18CC222R1C3 or NFM18CC223R1C3.

All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

The minimum CORECLK rise and fall times should also be observed. For the input clock timing requirements, see Section 4.7.4.4.

CAUTION

The PLL controller module as described in the TMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (SPRUGL3) includes a superset of features, some of which are not supported on the C6457 DSP. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the C6457 DSP. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

4.7.4.1 PLL1 Controller Device-Specific Information

4.7.4.1.1 Internal Clocks and Maximum Operating Frequencies

The main PLL, used to drive the core, the switch fabric, and a majority of the peripheral clocks (all but the DDR2 clock) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The main PLL controller has several SYSCLK outputs that are listed below, along with the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.

SYSREFCLK: Full-rate clock (GEM_CLK1) for C64x+ megamodule.
SYSCLK2: 1/2-rate clock (GEM_L2_CLK) used to clock the L2 and L2 powerdown controller.
SYSCLK3: 1/x-rate clock (GEM_TRACE_CLK) for emulation and trace logic of the DSP. The default rate for this clock is 1/3. This is programmable from /1 to /32, where this clock does not violate the maximum clock rate of 333 MHz. The data rate on the trace pins are 1/2 of this clock.
SYSCLK4: 1/3-rate clock (CHIP_CLK3) for the switched central resources (SCRs), EDMA3, VCP2, TCP2_A, TCP2_B, SRIO, as well as the data bus interfaces of the EMIFA and DDR2 memory controller.
SYSCLK5: 1/6-rate clock (CHIP_CLK6) for other peripherals (PLL controller, PSC, L3 ROM, McBSPs, Timer64s, EMAC, HPI, UTOPIA, I²C, and GPIO).
SYSCLK6: 1/y-rate clock (CHIP_CLKS) for an optional McBSP CLKS module input to drive the clock generator. The default for this clock is 1/10. This is programmable from /6 to /32, where this clock does not violate the maximum clock rate of 100 MHz. This clock is also output to the SYSCLKOUT pin.
SYSCLK7: 1/z-rate clock (EMIF_MCLK) for an optional internal clock for EMIFA. The default for this clock is 1/10. This is programmable from /6 to /32, where this clock does not violate the maximum clock rate of 166 MHz. The data rate at the pins must not violate 100 MHz.
SYSCLK8: 1/p-rate clock (SLOW_SYSCLK). The default for this clock is 1/10. This is programmable from /10 to /32.

NOTE

In case any of the other programmable SYSCLKs are set slower than 1/10 rate, then SYSCLK8 (SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the system.

Note that there is a minimum and maximum operating frequency for CORECLK(N|P), ALTCORECLK, SYSREFCLK, SYSCLK3, SYSCLK6, and SYSCLK7. The PLL1 controller must not be configured to exceed any of these constraints (certain combinations of external core clock input, internal dividers, and PLL multiply ratios might not be supported). For the PLL clocks input and output frequency ranges, see Table 4-22.

Table 4-22 Timing Requirements for Reset

CLOCK SIGNAL	MIN	MAX	UNIT
CORECLK(N\|P)	50	61.44	MHz
ALTCORECLK	50	61.44	MHz
SYSREFCLK	400	1200	MHz
SYSCLK3		333	MHz
SYSCLK6		100	MHz
SYSCLK7		166	MHz

4.7.4.1.2 PLL1 Controller Operating Modes

The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is generated from the device input clock CORECLK(N|P) using the divider POSTDIV and the PLL multiplier PLLM. In bypass mode, CORECLK(N|P) is fed directly to SYSREFCLK.

All hosts (HPI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed.

4.7.4.1.3 PLL1 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup. The PLL should not be operated until this stabilization time has expired.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time value, see Table 4-23.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The PLL1 lock time is given in Table 4-23.

Table 4-23 PLL1 Stabilization, Lock, and Reset Times

	MIN	MAX	UNIT
PLL stabilization time	100		µs
PLL lock time		2000 × C⁽¹⁾
PLL reset time	1000		ns

(1) C = CORECLK(N|P) cycle time in ns.

4.7.4.2 PLL1 Controller Memory Map

The memory map of the PLL1 controller is shown in Table 4-24. Note that only registers documented here are accessible on the C6457. Other addresses in the PLL1 controller memory map should not be modified.

Table 4-24 PLL1 Controller Registers (Including Reset Controller)

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
029A 0000 - 029A 00E3	-	Reserved
029A 00E4	RSTYPE	Reset Type Status Register (Reset Controller)
029A 00E8	RSTCTRL	Software Reset Control Register
029A 00EC	RSTCFG	Reset Configuration Register
029A 00F0 - 029A 00FF	-	Reserved
029A 0100	PLLCTL	PLL Control Register
029A 0104	-	Reserved
029A 0108	-	Reserved
029A 010C	-	Reserved
029A 0110	PLLM	PLL Multiplier Control Register
029A 0114	-	Reserved
029A 0118	-	Reserved
029A 011C	-	Reserved
029A 0120	PLLDIV3	PLL Controller Divider 3 Register
029A 0124	-	Reserved
029A 0128	POSTDIV	PLL Post-Divider Register
029A 012C	-	Reserved
029A 0130	-	Reserved
029A 0134	-	Reserved
029A 0138	PLLCMD	PLL Controller Command Register
029A 013C	PLLSTAT	PLL Controller Status Register
029A 0140	ALNCTL	PLL Controller Clock Align Control Register
029A 0144	DCHANGE	PLLDIV Ratio Change Status Register
029A 0148	-	Reserved
029A 014C	-	Reserved
029A 0150	SYSTAT	SYSCLK Status Register
029A 0154	-	Reserved
029A 0158	-	Reserved
029A 015C	-	Reserved
029A 0160 - 029A 0164	-	Reserved
029A 0168	PLLDIV6	PLL Controller Divider 6 Register
029A 016C	PLLDIV7	PLL Controller Divider 7 Register
029A 0170	PLLDIV8	PLL Controller Divider 8 Register
029A 0174 - 029B FFFF	-	Reserved

4.7.4.3 PLL1 Controller Registers

This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see theTMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (SPRUGL3).

NOTE

The PLL1 controller registers can be accessed by any master in the device.

CAUTION

Not all of the registers documented in the TMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (SPRUGL3) are supported on the C6457. Only those registers documented in this section are supported. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

4.7.4.3.1 PLL1 Control Register

The PLL1control register (PLLCTL) is shown in Figure 4-16 and described in Table 4-25.

Figure 4-16 PLL1 Control Register (PLLCTL) (Address - 029A 0100h)

Reserved

R-0

Reserved

Rsvd

Reserved

PLL
RST

Rsvd

PLLPWRDN

PLLEN

R-0

R/W-0

R-1

R/W-0

R/W-1

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-25 PLL1 Control Register (PLLCTL) Field Descriptions

Bit	Acronym	Description
31:8	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
7	Reserved	Reserved. Writes to this register must keep this bit as 0.
6	Reserved	Reserved. Read only. Always reads as 1. Writes have no effect.
5:4	Reserved	Reserved. Writes to this register must keep this bit as 0.
3	PLLRST	PLL reset bit 0 = PLL reset is released 1 = PLL reset is asserted
2	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
1	PLLPWRDN	PLL power-down mode select bit 0 = PLL is operational 1 = PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
0	PLLEN	PLL enable bit 0 = Bypass mode. Divider POSTDIV and PLL are bypassed. All the system clocks (SYSCLKn) are divided down directly from input reference clock. 1 = PLL mode. Divider POSTDIV and PLL are not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are divided down from PLL output.

4.7.4.3.2 PLL Multiplier Control Register

The PLL multiplier control register (PLLM) is shown in Figure 4-17 and described in Table 4-26. The PLLM register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits (RATIO) in the PLL controller post-divider register (POSTDIV).

Figure 4-17 PLL Multiplier Control Register (PLLM) (Address - 029A 0110h)

Reserved

R-0

Reserved

PLLM

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-26 PLL Multiplier Control Register (PLLM) Field Descriptions

Bit	Acronym	Description
31:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:0	PLLM	PLL multiplier bits. Defines the frequency multiplier of the input reference clock in conjunction with the PLL divider ratio bits (RATIO) in POSTDIV.
4:0	PLLM	000000 = × 1 000001 = × 2 000010 = × 3 000011 = × 4 000100 = × 5 000101 = × 6 000110 = × 7 000111 = × 8 001000 = × 9 001001 = × 10 001010 = × 11 001011 = × 12 001100 = × 13 001101 = × 14 001110 = × 15 001111 = × 16	010000 = × 17 010001 = × 18 010010 = × 19 010011 = × 20 010100 = × 21 010101 = × 22 010110 = × 23 010111 = × 24 011000 = × 25 011001 = × 26 011010 = × 27 011011 = × 28 011100 = × 29 011101 = × 30 011110 = × 31 011111 = × 32	100000 = × 33 100001 = × 34 100010 = × 35 100011 = × 36 100100 = × 37 100101 = × 38 100110 = × 39 100111 = × 40 101000 = × 41 101001 = × 42 101010 = × 43 101011 = × 44 101100 = × 45 101101 = × 46 101110 = × 47 101111 = × 48	110000 = × 49 110001 = × 50 110010 = × 51 110011 = × 52 110100 = × 53 110101 = × 54 110110 = × 55 110111 = × 56 111000 = × 57 111001 = × 58 111010 = × 59 111011 = × 60 111100 = × 61 111101 = × 62 111110 = × 63 111111 = × 64

4.7.4.3.3 PLL Post-Divider Control Register

The PLL post-divider control register (POSTDIV) is shown in Figure 4-18 and described in Table 4-27.

Figure 4-18 PLL Post-Divider Control Register (POSTDIV) (Address - 029A 0128)

Reserved

R-0

POSTDEN

Reserved

RATIO

R/W-1

R-0

R/W-2h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-27 PLL Post-Divider Control Register (POSTDIV) Field Descriptions

Bit	Acronym	Description
31:16	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
15	POSTDEN	Post-divider enable bit. 0 = Post-divider is disabled. No clock output. 1 = Post-divider is enabled.
14:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:0	RATIO	0 through 1Fh are divider ratio bits: 0 = ÷ 1. Divide frequency by 1. 1h = ÷ 2. Divide frequency by 2. 2h = ÷ 3. Divide frequency by 3. 3h through 1Fh = Reserved, do not use.

4.7.4.3.4 PLL Controller Divider 3 Register

The PLL controller divider 3 register (PLLDIV3) is shown in Figure 4-19 and described in Table 4-28.

Figure 4-19 PLL Controller Divider 3 Register (PLLDIV3) (Address - 029A 015Ch)

Reserved

R-0

D3EN

Reserved

RATIO

R/W-1

R-0

R/W-2h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-28 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions

Bit	Acronym	Description
31:16	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
15	D3EN	Divider 3 enable bit. 0 = Divider 3 is disabled. No clock output. 1 = Divider 3 is enabled.
14:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:0	RATIO	0 through 1Fh are divider ratio bits: 0 = ÷ 1. Divide frequency by 1. 1h = ÷ 2. Divide frequency by 2. 2h = ÷ 3. Divide frequency by 3. 3h = ÷ 4. Divide frequency by 4. 4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

4.7.4.3.5 PLL Controller Divider 6 Register

The PLL controller divider 6 register (PLLDIV6) is shown in Figure 4-20 and described in Table 4-29.

Figure 4-20 PLL Controller Divider 6 Register (PLLDIV6) Address - 029A 0168)

Reserved

R-0

D6EN

Reserved

RATIO

R/W-1

R-0

R/W-9h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-29 PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions

Bit	Acronym	Description
31:16	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
15	D6EN	Divider 6 enable bit. 0 = Divider 6 is disabled. No clock output. 1 = Divider 6 is enabled.
14:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:0	RATIO	0 through 1Fh are divider ratio bits: 0 = ÷ 1. Divide frequency by 1. 1h = ÷ 2. Divide frequency by 2. 2h = ÷ 3. Divide frequency by 3. 3h = ÷ 4. Divide frequency by 4. 4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

4.7.4.3.6 PLL Controller Divider 7 Register

The PLL controller divider 7 register (PLLDIV7) is shown in Figure 4-21 and described in Table 4-30.

Figure 4-21 PLL Controller Divider 7 Register (PLLDIV7) (Address - 029A 016Ch)

Reserved

R-0

D7EN

Reserved

RATIO

R/W-1

R-0

R/W-9h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-30 PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions

Bit	Acronym	Description
31:16	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
15	D7EN	Divider 7 enable bit. 0 = Divider 6 is disabled. No clock output. 1 = Divider 6 is enabled.
14:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:0	RATIO	0 through 1Fh are divider ratio bits: 0 = ÷ 1. Divide frequency by 1. 1h = ÷ 2. Divide frequency by 2. 2h = ÷ 3. Divide frequency by 3. 3h = ÷ 4. Divide frequency by 4. 4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

4.7.4.3.7 PLL Controller Divider 8 Register

The PLL controller divider 8 register (PLLDIV7) is shown in Figure 4-22 and described in Table 4-31.

Figure 4-22 PLL Controller Divider 8 Register (PLLDIV8) (Address - 029A 0170)

Reserved

R-0

D8EN

Reserved

RATIO

R/W-1

R-0

R/W-9h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-31 PLL Controller Divider 8 Register (PLLDIV8) Field Descriptions

Bit	Acronym	Description
31:16	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
15	D8EN	Divider 8 enable bit. 0 = Divider 6 is disabled. No clock output. 1 = Divider 6 is enabled.
14:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:0	RATIO	0 through 1Fh are divider ratio bits: 0 = ÷ 1. Divide frequency by 1. 1h = ÷ 2. Divide frequency by 2. 2h = ÷ 3. Divide frequency by 3. 3h = ÷ 4. Divide frequency by 4. 4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

4.7.4.3.8 PLL Controller Command Register

The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 4-23 and described in Table 4-32.

Figure 4-23 PLL Controller Command Register (PLLCMD) (Address - 029A 0138h)

Reserved

R-0

Reserved

GOSET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-32 PLL Controller Command Register (PLLCMD) Field Descriptions

Bit	Acronym	Description
31:2	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
1	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
0	GOSET	GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1 to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed. 0 = No effect. Write of 0 clears bit to 0. 1 = Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes of 1 can initiate the GO operation.

4.7.4.3.9 PLL Controller Status Register

The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 4-24 and described in Table 4-33.

Figure 4-24 PLL Controller Status Register (PLLSTAT) (Address - 029A 013C)

Reserved

R-0

Reserved

GOSTAT

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-33 PLL Controller Status Register (PLLSTAT) Field Descriptions

Bit	Acronym	Description
31:1	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
0	GOSTAT	GO operation status. 0 = GO operation is not in progress. SYSCLK divide ratios are not being changed. 1 = GO operation is in progress. SYSCLK divide ratios are being changed.

4.7.4.3.10 PLL Controller Clock Align Control Register

The PLL controller clock align control register (ALNCTL) is shown in Figure 4-25 and described in Table 4-34.

Figure 4-25 PLL Controller Clock Align Control Register (ALNCTL) (Address - 029A 0140)

Reserved

R-0

Reserved

ALN5

ALN4

Reserved

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-34 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Bit	Acronym	Description
31:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:3	ALNn	SYSCLKn alignment. Do not change the default values of these fields. 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set to 1, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set. 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set. The SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn
2:0	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.

4.7.4.3.11 PLLDIV Ratio Change Status Register

Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will change the divide ratio of only the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in Figure 4-26 and described in Table 4-35.

Figure 4-26 PLLDIV Divider Ratio Change Status Register (DCHANGE) (Address - 029A 0144)

Reserved

R-0

Reserved

SYS5

SYS4

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-35 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Bit	Acronym	Description
31:5	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4	SYS5	Identifies when the SYSCLK5 divide ratio has been modified. 0 = SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected. 1 = SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio.
3	SYS4	Identifies when the SYSCLK4 divide ratio has been modified. 0 = SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected. 1 = SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio.
2:0	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.

4.7.4.3.12 SYSCLK Status Register

The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is shown in Figure 4-27 and described in Table 4-36.

Figure 4-27 SYSCLK Status Register (SYSTAT) (Address - 029A 0150)

Reserved

R-0

Reserved

SYS5ON

SYS4ON

SYS3ON

SYS2ON

Rsvd

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-36 SYSCLK Status Register (SYSTAT) Field Descriptions

Bit	Acronym	Description
31:4	Reserved	Reserved. Read only. Always reads as 0. Writes have no effect.
4:1	SYSnON	SYSCLKn on status. 0 = SYSCLKn is gated. 1 = SYSCLKn is on.
0:	Reserved	Reserved. Read only. Always reads as 1. Writes have no effect.

4.7.4.4 PLL1 Controller Input and Output Electrical Data/Timing

Table 4-37 CORECLK(N|P) and ALTCORECLK Timing Requirements⁽¹⁾

NO.			MIN	MAX	UNIT
CORECLK(N\|P) and ALTCORECLK
1	t_c(SYSCLK)	Cycle time, CORECLK(N\|P) or ALTCORECLK	16.27	20.00	ns
2	t_w(SYSCLKH)	Pulse duration, CORECLK(N\|P) or ALTCORECLK high	0.45 x C₁		ns
3	t_w(SYSCLKL)	Pulse duration, CORECLK(N\|P) or ALTCORECLK low	0.45 x C₁		ns
4	t_t(SYSCLK)	Transition time, CORECLK(N\|P) or ALTCORECLK	50	1300	ps
5	t_j(SYSCLK)	Period Jitter (peak-to-peak), CORECLK(N\|P) or ALTCORECLK		100	ps
SYSCLKOUT
1	t_c(CKO)	Cycle time, SYSCLKOUT	10 x C₁	32 x C₁	ns
2	t_w(CKOH)	Pulse duration, SYSCLKOUT high	4 x C₁ - 0.7	32 x C₁ + 0.7	ns
3	t_w(CKOL)	Pulse duration, SYSCLKOUT low	4 x C₁ - 0.7	32 x C₁ + 0.7	ns
4	t_t(CKO)	Transition time, SYSCLKOUT		1.0	ns

(1) If CORECLKSEL = 0, C₁ = CORECLK(N|P) cycle time in ns. If CORECLKSEL = 1, C₁ = ALTCORECLK cycle time in ns.

SM320C6457-HIREL CORECLK_and_ALTCORECLK_Timing_6484.gif

Figure 4-28 CORECLK(N|P) and ALTCORECLK Timing

4.7.5 PLL2

The secondary PLL generates interface clocks for the DDR2 memory controller. Using the DDRCLKSEL pin the user can select the input source of PLL2 as either the DDRREFCLK or the ALTDDRCLK clock reference sources.

When coming out of power-on reset, PLL2 is enabled and initialized.

As shown in Figure 4-29, the PLL2 multiplier is fixed at a ×10 multiplier rate followed by a fixed /2 divider resulting in an effective x5 multiplier going to the DDR2PHY and attached DDR2 memory.

SM320C6457-HIREL PLL2_Block_Diagram_6484.gif

Figure 4-29 PLL2 Block Diagram

PLL2 power is supplied externally via the PLL2 power supply (PLLV₂). An external PLL filter circuit must be added to PLLV₂ as shown in Figure 4-29. The 1.8-V supply for the EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DV_DD18. TI requires EMI filter manufacturer Murata NFM18CC222R1C3 or NFM18CC223R1C3. For more information on the external PLL filter or the EMI filter, see the TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (SPRAAV7).

All PLL external components (capacitors and the EMI filter) should be placed as close to the C64x+ DSP device as possible. For the best performance, TI requires that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (capacitors and the EMI filter). The minimum CLKIN2 rise and fall times should also be observed.

4.7.5.1 PLL2 Device-Specific Information

4.7.5.1.1 Internal Clocks and Maximum Operating Frequencies

As shown in Figure 4-29, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2 memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT(N|P)0 and DDR2CLKOUT(N|P)1. Note that, internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK4 and PLL1 controller.

Note that there is a minimum and maximum operating frequency for DDRREFCLK and associated DDR2CLKOUT(N|P)0 and DDR2CLKOUT(N|P)1. For the PLL clocks input and output frequency ranges, see Table 4-38.

Table 4-38 PLL2 Clock Frequency Ranges

SIGNAL	MIN	MAX	UNIT
DDRREFCLK (PLLEN = 1)	40	66.67	MHz
DDR2CLKOUT0(P\|N) and DDR2CLKOUT1(P\|N)	200	333	MHz

4.7.5.1.2 PLL2 Operating Modes

Unlike the PLL1 which can operate in by-pass and PLL mode, the PLL2 only operates in PLL mode. In PLL mode, DDR2CLKOUT0(P|N) and DDR2CLKOUT1 (P|N) are generated by an effective x5 multiplier consisting of the PLL2 fixed x10 multiplier followed by a /2 divider.

The PLL2 is affected by power-on reset. During power-on resets, the internal clocks of the PLL2 are affected as described in Section 4.7.3.

PLL2 is unlocked only during the power-up sequence (see Section 4.7.3) and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other reset

4.7.5.2 PLL2 Input Clock Electrical Data/Timing

Table 4-39 Timing Requirements for DDRREFCLK(N|P) and ALTDDRCLK⁽¹⁾

(see Figure 4-30)

NO.			MIN	MAX	UNIT
1	t_c(CLKIN2)	Cycle time, DDRREFCLK(N\|P) or ALTDDRCLK	15.00	25.00	ns
2	t_w(CLKIN2H)	Pulse duration, DDRREFCLK(N\|P) or ALTDDRCLK high	0.45 × C₂	0.55 × C₂	ns
3	t_w(CLKIN2L)	Pulse duration, DDRREFCLK(N\|P) or ALTDDRCLK low	0.45 × C₂	0.55 × C₂	ns
4	t_t(CLKIN2)	Transition time, DDRREFCLK(N\|P) or ALTDDRCLK	50	1300	ps
5	t_J(CLKIN2)	Period jitter (peak-to-peak), DDRREFCLK(N\|P) or ALTDDRCLK		0.02 × tc_(CLKIN2)

(1) If DDRCLKSEL = 0, C₂ = DDRREFCLK(N|P) cycle time in ns. If DDRCLKSEL = 1, C₂ = ALTDDRCLK cycle time in ns.

SM320C6457-HIREL DDRREFCLK_Timing_6484.gif

Figure 4-30 DDRREFCLK(N|P) Timing

4.7.6 DDR2 Memory Controller

The 32-bit DDR2 Memory Controller bus of the C6457 is used to interface to JESD79-2B standard-compliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM devices; it does not share the bus with any other types of peripherals. The decoupling of DDR2 memories from other devices both simplifies board design and provides I/O concurrency from a second external memory interface, EMIFA.

The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum throughput of the DDR2 bus. The clock frequency of the DDR2 bus is equal to the CLKIN2 frequency multiplied by 10. The internal data bus clock frequency of the DDR2 Memory Controller is fixed at a divide-by-three ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the two bus frequencies. The DDR2 bus is designed to sustain a throughput of up to 2.67 Gbyte/sec at a 667-MHz data rate (333-MHz clock rate) as long as data requests are pending in the DDR2 Memory Controller.

4.7.6.1 DDR2 Memory Controller Device-Specific Information

The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces such as EMIF, McBSP, and HPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models.

For the C6457 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met. The complete DDR2 system solution is documented in the TMS320C6457 DDR2 Implementation Guidelines application report (SPRAB21).

TI supports only designs that follow the board design guidelines outlined in the application report.

The DDR2 memory controller on the C6457 device supports the following memory topologies:

A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.
A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.

A race condition may exist when certain masters write data to the DDR2 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

Perform the required write.
Perform a dummy write to the DDR2 memory controller module ID and revision register.
Perform a dummy read to the DDR2 memory controller module ID and revision register.
Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

4.7.6.2 DDR2 Memory Controller Peripheral Register Description(s)

Table 4-40 DDR2 Memory Controller Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
7800 0000	MIDR	DDR2 Memory Controller Module and Revision Register
7800 0004	DMCSTAT	DDR2 Memory Controller Status Register
7800 0008	SDCFG	DDR2 Memory Controller SDRAM Configuration Register
7800 000C	SDRFC	DDR2 Memory Controller SDRAM Refresh Control Register
7800 0010	SDTIM1	DDR2 Memory Controller SDRAM Timing 1 Register
7800 0014	SDTIM2	DDR2 Memory Controller SDRAM Timing 2 Register
7800 0018	-	Reserved
7800 0020	BPRIO	DDR2 Memory Controller Burst Priority Register
7800 0024 - 7800 004C	-	Reserved
7800 0050 - 7800 0078	-	Reserved
7800 007C - 7800 00BC	-	Reserved
7800 00C0 - 7800 00E0	-	Reserved
7800 00E4	DMCCTL	DDR2 Memory Controller Control Register
7800 00E8 - 7FFF FFFF	-	Reserved

4.7.6.3 DDR2 Memory Controller Electrical Data/Timing

The TMS320C6457 DDR2 Implementation Guidelines application report (SPRAB21) specifies a complete DDR2 interface solution for the C6457 as well as a list of compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

4.7.7 External Memory Interface A (EMIFA)

The EMIFA can interface to a variety of external devices or ASICs, including:

Pipelined and flow-through synchronous-burst SRAM (SBSRAM)
ZBT (zero bus turnaround) SRAM and late write SRAM
Synchronous FIFOs
Asynchronous memory, including SRAM, ROM, and Flash

For more information about the EMIF peripheral, see the TMS320C6457 DSP External Memory Interface (EMIF) User's Guide (SPRUGK2).

4.7.7.1 EMIFA Device-Specific Information

Timing analysis must be done to verify all AC timings are met. TI recommends using I/O buffer information specification (IBIS) to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (for the EMIF output signals, see Table 3-2).

A race condition may exist when certain masters write data to the EMIFA. For example, if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

Perform the required write.
Perform a dummy write to the EMIFA module ID and revision register.
Perform a dummy read to the EMIFA module ID and revision register.
Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

4.7.7.2 EMIFA Peripheral Register Description(s)

Table 4-41 EMIFA Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
7000 0000	MIDR	Module ID and Revision Register
7000 0004	STAT	Status Register
7000 0008	-	Reserved
7000 000C - 7000 001C	-	Reserved
7000 0020	BURST_PRIO	Burst Priority Register
7000 0024 - 7000 004C	-	Reserved
7000 0050 - 7000 007C	-	Reserved
7000 0080	CE2CFG	EMIFA CE2 Configuration Register
7000 0084	CE3CFG	EMIFA CE3 Configuration Register
7000 0088	CE4CFG	EMIFA CE4 Configuration Register
7000 008C	CE5CFG	EMIFA CE5 Configuration Register
7000 0090 - 7000 009C	-	Reserved
7000 00A0	AWCC	EMIFA Async Wait Cycle Configuration Register
7000 00A4 - 7000 00BC	-	Reserved
7000 00C0	INTRAW	EMIFA Interrupt RAW Register
7000 00C4	INTMSK	EMIFA Interrupt Masked Register
7000 00C8	INTMSKSET	EMIFA Interrupt Mask Set Register
7000 00CC	INTMSKCLR	EMIFA Interrupt Mask Clear Register
7000 00D0 - 7000 00DC	-	Reserved
7000 00E0 - 77FF FFFF	-	Reserved

4.7.7.3 EMIFA Electrical Data/Timing

This section describes the electrical timing for the EMIFA peripheral.

4.7.7.3.1 AECLKIN and AECLKOUT Timing

Table 4-42 EMIFA AECLKIN Timing Requirements⁽¹⁾⁽²⁾

(see Figure 4-31)

NO.			MIN	MAX	UNIT
1	t_c(EKI)	Cycle time, AECLKIN	10⁽³⁾	40	ns
2	t_w(EKIH)	Pulse duration, AECLKIN high	2.7		ns
3	t_w(EKIL)	Pulse duration, AECLKIN low	2.7		ns
4	t_t(EKI)	Transition time, AECLKIN		2	ns
5	t_j(EKI)	Period Jitter, AECLKIN		0.02E⁽⁴⁾	ns

(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

(2) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based on internal logic speed; the maximum usable speed of the EMIF may be lower due to AC timing requirements.

(4) This timing applies only when AECLKIN is used for EMIFA.

SM320C6457-HIREL EMIFA_AECLKIN_Timing_6484.gif

Figure 4-31 EMIFA AECLKIN Timing

Table 4-43 EMIFA AECLKOUT Switching Characteristics⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

(see Figure 4-32)

NO.	PARAMETER		MIN	MAX	UNIT
1	t_c(EKO)	Cycle time, AECLKOUT	E - 0.7	E + 0.7	ns
2	t_w(EKOH)	Pulse duration, AECLKOUT high	EH - 0.7	EH + 0.7	ns
3	t_w(EKOL)	Pulse duration, AECLKOUT low	EL - 0.7	EL + 0.7	ns
4	t_t(EKO)	Transition time, AECLKOUT		1	ns
5	t_d(EKIH-EKOH)	Delay time, AECLKIN high to AECLKOUT high	1	8	ns
6	t_d(EKIL-EKOL)	Delay time, AECLKIN low to AECLKOUT low	1	8	ns

(1) Over Recommended Operating Conditions.

(2) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(3) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.

(4) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

SM320C6457-HIREL EMIFA_AECLKOUT_Timing_6484.gif

Figure 4-32 EMIFA AECLKOUT Timing

4.7.7.3.2 Asynchronous Memory Timing

This section describes the asynchronous EMIFA Read, Write, EM_WAIT Read and EM_WAIT Write timing requirements and switching characteristics.

Table 4-44 EMIFA Asynchronous Memory Read Switching Characteristics⁽¹⁾⁽²⁾

(see Figure 4-33)

NO.	PARAMETER		MIN	MAX	UNIT
3	t_c(ACEL-read)	EMIF read cycle time when ew = 0. Meaning not in extended wait mode	(RS + RST + RH + 3) × E - 1	(RS + RST + RH + 3) × E + 1	ns
3	t_c(ACEL-read)	EMIF read cycle time when ew = 1. Meaning extended wait mode enabled	(RS + RST + RH + 3) × E - 1	(RS + RST + RH + 3) × E + 1	ns
4	t_{osu(ACEL-AAOEL)}	Output setup time from ACEn low to AAOE/ASOE low. SS = 0, not in select strobe mode	(RS+1) × E-1.5		ns
4	t_{osu(ACEL-AAOEL)}	Output setup time from ACEn low to AAOE/ASOE low. SS = 1, in select strobe mode	(RS+1) × E-1.5		ns
5	t_{oh(AAOEH-ACEH)}	Output hold time from AAOE/ASOE high to ACEn high. SS = 0, not in select strobe mode	(RS+1) × E-1.9		ns
5	t_{oh(AAOEH-ACEH)}	Output hold time from AAOE/ASOE high to ACEn high. SS = 1, in select strobe mode	(RS+1) × E-1.9		ns
6	t_{osu(ABAV-AAOEL)}	Output setup time from ABA valid to AAOE/ASOE low	(RS+1) × E-1.5		ns
7	_{toh(AAOEH-ABAV)}	Output hold time from AAOE/ASOE high to BA invalid	(RS+1) × E-1.9		ns
8	t_{osu(AEAV-OEL)}	Output setup time from AEA valid to AAOE/ASOE low	(RS+1) × E-1.5		ns
9	t_{oh(AAOEH-AEAV)}	Output hold time from AAOE/ASOE high to AEA invalid	(RS+1) × E-1.9		ns
10	t_w(AAOEL)	AAOE/ASOE active time low, when ew = 0, extended wait mode is disabled	(RST+1) × E - 6	(RST+1) × E + 6	ns
10	t_w(AAOEL)	AAOE/ASOE active time low, when ew = 1, extended wait mode is enabled	(RST+1) × E - 6	(RST+1) × E + 6	ns

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(2) RS, RST, RH, WS, WST, WH, and TA are all based on the memory mapped register values. This means that the actual value listed here is the value in EMIF cycles - 1.
Example: For read setup of 1 EMIF cycle, RS = 0.

Table 4-45 EMIFA Asynchronous Memory Read Timing Requirements

(see Figure 4-33)

NO.			MIN	MAX	UNIT
12	t_{su(AEDV-AAOEH)}	Input setup time from AED valid to AAOE/ASOE high	6.5		ns
13	t_{h(AAOEH-AEDV)}	Input hold time from AAOE/ASOE high to AED invalid	0		ns

SM320C6457-HIREL EMIFA_Asynchronous_Memory_Read_Timing_6484.gif

Figure 4-33 EMIFA Asynchronous Memory Read Timing

Table 4-46 EMIFA Asynchronous Memory Write Timing Requirements⁽¹⁾⁽²⁾

(see Figure 4-34)

NO.			MIN	MAX	UNIT
15	t_{c(ACEL-write)}	EMIF write cycle time when ew = 0, extended wait mode	(WS + WST + WH + TA + 4) × E - 1	(WS + WST + WH + TA + 4) × E + 1	ns
15	t_{c(ACEL-write)}	EMIF write cycle time when ew = 1, extended wait mode is enabled.	(WS + WST + WH + TA + 4) × E - 1	(WS + WST + WH + TA + 4) × E + 1	ns
16	t_{osu(ACEL-AAWEL)}	Output setup time from ACEn low to ASWE/AAWE low. SS = 0, not in select strobe mode	(WS+1) × E-1.7		ns
16	t_{osu(ACEL-AAWEL)}	Output setup time from ACEn low to ASWE/AAWE low. SS = 1, in select strobe mode	(WS+1) × E-1.7		ns
17	t_{oh(AAWEH-ACEH)}	Output hold time from ASWE/AAWE high to ACEn high. SS = 0, not in select strobe mode	(WS+1) × E-1.8		ns
17	t_{oh(AAWEH-ACEH)}	Output hold time from ASWE/AAWE high to ACEn high. SS = 1, in select strobe mode	(WS+1) × E-1.8		ns
18	t_{osu(WV-AAWEL)}	Output setup time from AR/W valid to ASWE/AAWE low	(WS+1) × E-1.7		ns
19	t_{oh(AAWEH-WIV)}	Output hold time from ASWE/AAWE high to AR/W invalid	(WS+1) × E-1.8		ns
20	t_{osu(ABAV-AAWEL)}	Output setup time from BA valid to ASWE/AAWE low	(WS+1) × E-1.7		ns
21	t_{oh(AAWEH-ABAIV)}	Output hold time from ASWE/AAWE high to ABA invalid	(WS+1) × E-1.8		ns
22	t_{osu(AEAV-AAWEL)}	Output setup time from AEA valid to ASWE/AAWE low	(WS+1) × E-1.7		ns
23	t_{oh(AAWEH-AEAIV)}	Output hold time from ASWE/AAWE high to AEA invalid	(WS+1) × E-1.8		ns
24	t_w(AAWEL)	ASWE/AAWE active time low, when ew = 0. Extended wait mode is disabled.	(WST+1) × E - 5.8		ns
24	t_w(AAWEL)	ASWE/AAWE active time low, when ew = 1. Extended wait mode is enabled.	(WST+1) × E - 5.8		ns
26	t_{osu(AEDV-AAWEL)}	Output setup time from AED valid to ASWE/AAWE low	(WS+1) × E-5.0		ns
27	t_{oh(AAWEH-AEDIV)}	Output hold time from ASWE/AAWE high to AED invalid	(WS+1) × E-2.5		ns

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

SM320C6457-HIREL EMIFA_Asynchronous_Memory_Write_Timing_6484.gif

Figure 4-34 EMIFA Asynchronous Memory Write Timing

Table 4-47 EMIFA EM_Wait Read Timing Requirements⁽¹⁾

(see Figure 4-35)

NO.			MIN	MAX	UNIT
2	t_w(AARDY)	Pulse duration, AARDY assertion and deassertion minimum time		2E
14	t_{d(AARDY-AAOEH)}	Setup time, AARDY asserted before AAOE high		4E + 6

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

Table 4-48 EMIFA EM_Wait Read Switching Characteristics⁽¹⁾

(see Figure 4-35)

NO.	PARAMETER		MIN	MAX	UNIT
11	t_{d(AARDYH-AAOEH)}	Delay time from AARDY deasserted to AAOE/ASOE high		4E + 6

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

SM320C6457-HIREL EMIFA_EM_Wait_Read_Timing_6484.gif

Figure 4-35 EMIFA EM_Wait Read Timing

Table 4-49 EMIFA EM_Wait Write Timing Requirements

(see Figure 4-36)

NO.			MAX	UNIT
2	t_w(AARDY)	Pulse duration, AARDY assertion and deassertion minimum time		2E
25	t_{d(AARDYH-AAWEH)}	Delay time from AARDY deasserted to ASWE/AAWE high	4E + 6.0
28	t_{su(AARDY-AAWEH)}	Setup time, AARDY asserted before ASWE/AAWE high	4E + 6.0

SM320C6457-HIREL EMIFA_EM_Wait_Write_Timing_6484.gif

Figure 4-36 EMIFA EM_Wait Write Timing

4.7.7.3.3 Programmable Synchronous Interface Timing

This section describes the synchronous EMIFA Read and Write timing requirements.

The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG) (see Table 4-51) and via the EMIFA Chip Select n Configuration Register (CESECn):

Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).
Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).

Figure 4-37, Figure 4-38, and Figure 4-39 are given as examples diagrams depicting some of the programmable options.

In Figure 4-37, R_LTNCY = 2, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
In Figure 4-38, W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
In Figure 4-39, W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

Table 4-50 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 4-37)

NO.			MIN	MAX	UNIT
6	t_su(EDV-EKOH)	Setup time, read AEDx valid before AECLKOUT high	2		ns
7	t_h(EKOH-EDV)	Hold time, read AEDx valid after AECLKOUT high	1.5		ns

Table 4-51 Switching Characteristics for Programmable Synchronous Interface Cycles for EMIFA Module⁽¹⁾

(see Figure 4-37, Figure 4-38, and Figure 4-39)

NO.	PARAMETER		MIN	MAX	UNIT
1	t_d(EKOH-CEV)	Delay time, AECLKOUT high to ACEx valid	1.3	4.9	ns
2	t_d(EKOH-BEV)	Delay time, AECLKOUT high to ABEx valid		4.9	ns
3	t_d(EKOH-BEIV)	Delay time, AECLKOUT high to ABEx invalid	1.3		ns
4	t_d(EKOH-EAV)	Delay time, AECLKOUT high to AEAx valid		4.9	ns
5	t_d(EKOH-EAIV)	Delay time, AECLKOUT high to AEAx invalid	1.3		ns
8	t_d(EKOH-ADSV)	Delay time, AECLKOUT high to ASADS/ASRE valid	1.3	4.9	ns
9	t_d(EKOH-OEV)	Delay time, AECLKOUT high to ASOE valid	1.3	4.9	ns
10	t_d(EKOH-EDV)	Delay time, AECLKOUT high to AEDx valid		5.2	ns
11	t_d(EKOH-EDIV)	Delay time, AECLKOUT high to AEDx invalid	1.3		ns
12	t_d(EKOH-WEV)	Delay time, AECLKOUT high to ASWE valid	1.3	4.9	ns

(1) Over recommended operating conditions.

SM320C6457-HIREL EMIFA_Programmable_Sync_IF_Read_Timing_Lat=2_6484.gif

Figure 4-37 EMIFA Programmable Synchronous Interface Read Timing (With Read Latency = 2)^(A)

(A) In this figure R_LTNCY = 2, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

(B) AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

SM320C6457-HIREL EMIFA_Programmable_write_timing.gif

Figure 4-38 EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 0)^(A)

(A) In this figure W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

(B) AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

SM320C6457-HIREL EMIFA_Programmable_Sync_IF_Write_Timing_Lat=1_6484.gif

Figure 4-39 EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 1)^(A)

(A) In this figure W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

(B) AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

4.7.8 I²C Peripheral

The inter-integrated circuit (I²C) module provides an interface between a C64x+ DSP and other devices compliant with Philips Semiconductors Inter-IC bus (I²C bus) specification version 2.1 and connected by way of an I²C bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I²C module.

4.7.8.1 I²C Device-Specific Information

The C6457 device includes an I²C peripheral module. NOTE: when using the I²C module, ensure there are external pullup resistors on the SDA and SCL pins.

The I²C modules on the C6457 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface.

The I²C port supports:

Compatible with Philips I²C specification revision 2.1 (January 2000)
Fast mode up to 400 Kbps (no fail-safe I/O buffers)
Noise filter to remove noise 50 ns or less
7-bit and 10-bit device addressing modes
Multi-master (transmit/receive) and slave (transmit/receive) functionality
Events: DMA, interrupt, or polling
Slew-rate limited open-drain output buffers

Figure 4-40 shows a block diagram of the I²C module.

SM320C6457-HIREL I2C_Module_Block_Diagram_6484.gif

Figure 4-40 I²C Module Block Diagram

4.7.8.2 I²C Peripheral Register Description(s)

Table 4-52 I²C Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02B0 4000	ICOAR	I²C own address register
02B0 4004	ICIMR	I²C interrupt mask/status register
02B0 4008	ICSTR	I²C interrupt status register
02B0 400C	ICCLKL	I²C clock low-time divider register
02B0 4010	ICCLKH	I²C clock high-time divider register
02B0 4014	ICCNT	I²C data count register
02B0 4018	ICDRR	I²C data receive register
02B0 401C	ICSAR	I²C slave address register
02B0 4020	ICDXR	I²C data transmit register
02B0 4024	ICMDR	I²C mode register
02B0 4028	ICIVR	I²C interrupt vector register
02B0 402C	ICEMDR	I²C extended mode register
02B0 4030	ICPSC	I²C prescaler register
02B0 4034	ICPID1	I²C peripheral identification register 1 [Value: 0x0000 0105]
02B0 4038	ICPID2	I²C peripheral identification register 2 [Value: 0x0000 0005]
02B0 403C - 02B0 405C	-	Reserved
02B0 4060 - 02B3 407F	-	Reserved
02B0 4080 - 02B3 FFFF	-	Reserved

4.7.8.3 I²C Electrical Data/Timing

4.7.8.3.1 Inter-Integrated Circuits (I²C) Timing

Table 4-53 I²C Timing Requirements⁽¹⁾

(see Figure 4-41)

NO.			STANDARD MODE		FAST MODE		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
1	t_c(SCL)	Cycle time, SCL	10		2.5		us
2	t_{su(SCLH-SDAL)}	Setup time, SCL high before SDA low (for a repeated START condition)	4.7		0.6		us
3	t_h(SDAL-SCLL)	Hold time, SCL low after SDA low (for a START and a repeated START condition)	4		0.6		us
4	t_w(SCLL)	Pulse duration, SCL low	4.7		1.3		us
5	t_w(SCLH)	Pulse duration, SCL high	4		0.6		us
6	t_{su(SDAV-SCLH)}	Setup time, SDA valid before SCL high	250		100⁽²⁾		ns
7	t_h(SCLL-SDAV)	Hold time, SDA valid after SCL low (For I²C bus devices)	0⁽³⁾	3.45	0⁽³⁾	0.9⁽⁴⁾	us
8	t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions	4.7		1.3		us
9	t_r(SDA)	Rise time, SDA		1000	20 + 0.1C_b⁽⁵⁾	300	ns
10	t_r(SCL)	Rise time, SCL		1000	20 + 0.1C_b⁽⁵⁾	300	ns
11	t_f(SDA)	Fall time, SDA		300	20 + 0.1C_b⁽⁵⁾	300	ns
12	t_f(SCL)	Fall time, SCL		300	20 + 0.1C_b⁽⁵⁾	300	ns
13	t_{su(SCLH-SDAH)}	Setup time, SCL high before SDA high (for STOP condition)	4		0.6		us
14	t_w(SP)	Pulse duration, spike (must be suppressed)			0	50	ns
15	C_b⁽⁵⁾	Capacitive load for each bus line		400		400	pF

(1) The I²C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down

(2) A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-Bus Specification) before the SCL line is released.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

SM320C6457-HIREL I2C_Receive_Timing_6484.gif

Figure 4-41 I²C Receive Timing

Table 4-54 I²C Switching Characteristics⁽¹⁾

(see Figure 4-42)

NO.	PARAMETER		STANDARD MODE		FAST MODE		UNITS
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNITS
16	t_c(SCL)	Cycle time, SCL	10		2.5		ms
17	t_{su(SCLH-SDAL)}	Setup time, SCL high to SDA low (for a repeated START condition)	4.7		0.6		ms
18	t_h(SDAL-SCLL)	Hold time, SDA low after SCL low (for a START and a repeated START condition)	4		0.6		ms
19	t_w(SCLL)	Pulse duration, SCL low	4.7		1.3		ms
20	t_w(SCLH)	Pulse duration, SCL high	4		0.6		ms
21	t_d(SDAV-SDLH)	Delay time, SDA valid to SCL high	250		100		ns
22	t_v(SDLL-SDAV)	Valid time, SDA valid after SCL low (For I²C bus devices)	0		0	0.9	ms
23	t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions	4.7		1.3		ms
24	t_r(SDA)	Rise time, SDA		1000	20 + 0.1C_b⁽¹⁾	300	ns
25	t_r(SCL)	Rise time, SCL		1000	20 + 0.1C_b⁽¹⁾	300	ns
26	t_f(SDA)	Fall time, SDA		300	20 + 0.1C_b⁽¹⁾	300	ns
27	t_f(SCL)	Fall time, SCL		300	20 + 0.1C_b⁽¹⁾	300	ns
28	t_d(SCLH-SDAH)	Delay time, SCL high to SDA high (for STOP condition)	4		0.6		ms
29	C_p	Capacitance for each I²C pin		10		10	pF

(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

SM320C6457-HIREL I2C_Transmit_Timing_6484.gif

Figure 4-42 I²C Transmit Timing

4.7.9 Host-Port Interface (HPI) Peripheral

4.7.9.1 HPI Device-Specific Information

The C6457 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32). The HPIWIDTH pin allows the user configuration of the HPI as a 16-bit or 32-bit peripheral.

Table 4-55 HPIWIDTH Selection

CONFIGURATION PIN SETTING	PERIPHERAL FUNCTION SELECTED
HPIWIDTH	HPI DATA LOWER	HPI DATA UPPER
0 (default is HPI16 mode)	Enabled	Hi-Z
1 (HPI32 mode)	Enabled	Enabled

Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the C6457.

An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.

4.7.9.2 HPI Peripheral Register Description(s)

Table 4-56 HPI Control Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME	COMMENTS
0288 0000	-	Reserved
0288 0004	PWREMU _MGMT	HPI power and emulation management register	The CPU has read/write access to the PWREMU_MGMT register; the Host does not have any access to this register.
0288 0008 - 0288 0024	-	Reserved
0288 0028	-	Reserved
0288 002C	-	Reserved
0288 0030	HPIC	HPI control register	The Host and the CPU have read/write access to the HPIC register.⁽¹⁾
0288 0034	HPIA (HPIAW)⁽²⁾	HPI address register (Write)	The Host has read/write access to the HPIA registers. The CPU has only read access to the HPIA registers.
0288 0038	HPIA (HPIAR)⁽²⁾	HPI address register (Read)
0288 000C - 028B 007F	-	Reserved
0288 0080 - 028B FFFF	-	Reserved

(1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an interrupt from the host.

(2) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes, see the TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

4.7.9.3 HPI Electrical Data/Timing

Table 4-57 Host-Port Interface Timing Requirements⁽¹⁾⁽²⁾

(see Table 4-58 and see Figure 4-43, Figure 4-44, Figure 4-45, Figure 4-46, Figure 4-47, Figure 4-48, Figure 4-49, and Figure 4-50)

NO.			MIN	UNIT
9	t_{su(HASL-HSTBL)}	Setup time, HAS low before HSTROBE low	5	ns
10	t_{h(HSTBL-HASL)}	Hold time, HAS low after HSTROBE low	2	ns
11	t_{su(SELV-HASL)}	Setup time, select signals⁽³⁾ valid before HAS low	5	ns
12	t_h(HASL-SELV)	Hold time, select signals⁽³⁾ valid after HAS low	5	ns
13	t_w(HSTBL)	Pulse duration, HSTROBE low	15	ns
14	t_w(HSTBH)	Pulse duration, HSTROBE high between consecutive accesses	2M	ns
15	t_{su(SELV-HSTBL)}	Setup time, select signals⁽³⁾ valid before HSTROBE low	5	ns
16	t_{h(HSTBL-SELV)}	Hold time, select signals⁽³⁾ valid after HSTROBE low	5	ns
17	t_{su(HDV-HSTBH)}	Setup time, host data valid before HSTROBE high	5	ns
18	t_h(HSTBH-HDV)	Hold time, host data valid after HSTROBE high	1	ns
37	t_{su(HCSL-HSTBL)}	Setup time, HCS low before HSTROBE low	0	ns
38	t_{h(HRDYL-HSTBL)}	Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly.	1.1	ns

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2) M = SYSCLK5 period = 6 ÷ CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

Table 4-58 Host-Port Interface Switching Characteristics⁽¹⁾⁽²⁾

(see Table 4-57 and see Figure 4-43, Figure 4-44, Figure 4-45, Figure 4-46, Figure 4-47, Figure 4-48, Figure 4-49, and Figure 4-50)

NO.	PARAMETER			MIN	MAX	UNIT
1	t_d(HSTBL-HDV)	Delay time, HSTROBE low to DSP data valid	Case 1. HPIC or HPIA read	1	15	ns
			Case 2. HPID read with no auto-increment⁽³⁾		9 × M + 20
			Case 3. HPID read with auto-increment and read FIFO initially empty⁽³⁾		9 × M + 20
			Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO	1	15
2	t_{dis(HSTBH-HDV)}	Disable time, HD high-impedance from HSTROBE high		1	4	ns
3	t_en(HSTBL-HD)	Enable time, HD driven from HSTROBE low		3	15	ns
4	t_{d(HSTBL-HRDYH)}	Delay time, HSTROBE low to HRDY high			12	ns
5	t_{d(HSTBH-HRDYH)}	Delay time, HSTROBE high to HRDY high			12	ns
6	t_{d(HSTBL-HRDYL)}	Delay time, HSTROBE low to HRDY low	Case 1. HPID read with no auto-increment⁽³⁾		10 × M + 20	ns
6	t_{d(HSTBL-HRDYL)}	Delay time, HSTROBE low to HRDY low	Case 2. HPID read with auto-increment and read FIFO initially empty⁽³⁾		10 × M + 20	ns
7	t_d(HDV-HRDYL)	Delay time, HD valid to HRDY low		0		ns
34	t_{d(HSTBH-HRDYL)}	Delay time, HSTROBE high to HRDY low	Case 1. HPIA write⁽³⁾		5 × M + 20	ns
34	t_{d(HSTBH-HRDYL)}	Delay time, HSTROBE high to HRDY low	Case 2. HPID write with no auto-increment⁽³⁾		5 × M + 20	ns
35	t_{d(HSTBL-HRDYL)}	Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not empty⁽³⁾			40 × M + 20	ns
36	t_{d(HASL-HRDYH)}	Delay time, HAS low to HRDY high			12	ns

(1) M = SYSCLK5 period = 6 ÷ CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.

SM320C6457-HIREL HPI16_Read_Timing_HAS_Not_Used_6484.gif

Figure 4-43 HPI16 Read Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

SM320C6457-HIREL HPI16_Read_Timing_HAS_Used_6484.gif

Figure 4-44 HPI16 Read Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

SM320C6457-HIREL HPI16_Write_Timing_HAS_Not_Used_6484.gif

Figure 4-45 HPI16 Write Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

SM320C6457-HIREL HPI16_Write_Timing_HAS_Used_6484.gif

Figure 4-46 HPI16 Write Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

SM320C6457-HIREL HPI32_Read_Timing_HAS_Not_Used_6484.gif

Figure 4-47 HPI32 Read Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

SM320C6457-HIREL HPI32_Read_Timing_HAS_Used_6484.gif

Figure 4-48 HPI32 Read Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

SM320C6457-HIREL HPI32_Write_Timing_HAS_Not_Used_6484.gif

Figure 4-49 HPI32 Write Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

SM320C6457-HIREL HPI32_Write_Timing_HAS_Used_6484.gif

Figure 4-50 HPI32 Write Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

4.7.10 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
External shift clock or an internal, programmable frequency shift clock for data transfer

For more detailed information on the McBSP peripheral, see the TMS320C6457 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (SPRUGK8).

4.7.10.1 McBSP Device-Specific Information

The CLKS signal for MCBSP0 and MCBSP1 can be sourced from an external pin or by the PLL1 controller; for details, see Section 4.7.4. If the clock from the PLL1 controller is used, the clock is shared between the two McBSPs.

4.7.10.1.1 McBSP Peripheral Register Description(s)

Table 4-59 McBSP 0 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
028C 0000	DRR0	McBSP0 Data Receive Register via Configuration Bus⁽¹⁾
3000 0000	DRR0	McBSP0 Data Receive Register via EDMA3 Bus
028C 0004	DXR0	McBSP0 Data Transmit Register via Configuration Bus
3000 0010	DXR0	McBSP0 Data Transmit Register via EDMA Bus
028C 0008	SPCR0	McBSP0 Serial Port Control Register
028C 000C	RCR0	McBSP0 Receive Control Register
028C 0010	XCR0	McBSP0 Transmit Control Register
028C 0014	SRGR0	McBSP0 Sample Rate Generator register
028C 0018	MCR0	McBSP0 Multichannel Control Register
028C 001C	RCERE00	McBSP0 Enhanced Receive Channel Enable Register 0 Partition A/B
028C 0020	XCERE00	McBSP0 Enhanced Transmit Channel Enable Register 0 Partition A/B
028C 0024	PCR0	McBSP0 Pin Control Register
028C 0028	RCERE10	McBSP0 Enhanced Receive Channel Enable Register 1 Partition C/D
028C 002C	XCERE10	McBSP0 Enhanced Transmit Channel Enable Register 1 Partition C/D
028C 0030	RCERE20	McBSP0 Enhanced Receive Channel Enable Register 2 Partition E/F
028C 0034	XCERE20	McBSP0 Enhanced Transmit Channel Enable Register 2 Partition E/F
028C 0038	RCERE30	McBSP0 Enhanced Receive Channel Enable Register 3 Partition G/H
028C 003C	XCERE30	McBSP0 Enhanced Transmit Channel Enable Register 3 Partition G/H
028C 0040 - 028F FFFF	-	Reserved

(1) The CPU and EDMA3 controller can only read the register, they cannot write to it.

Table 4-60 McBSP 1 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
0290 0000	DRR1	McBSP1 Data Receive Register via Configuration Bus(1)
3400 0000	DRR1	McBSP1 Data Receive Register via EDMA bus
0290 0004	DXR1	McBSP1 Data Transmit Register via configuration bus
3400 0010	DXR1	McBSP1 Data Transmit Register via EDMA bus
0290 0008	SPCR1	McBSP1 serial port control register
0290 000C	RCR1	McBSP1 Receive Control Register
0290 0010	XCR1	McBSP1 Transmit Control Register
0290 0014	SRGR1	McBSP1 sample rate generator register
0290 0018	MCR1	McBSP1 multichannel control register
0290 001C	RCERE01	McBSP1 Enhanced Receive Channel Enable Register 0 Partition A/B
0290 0020	XCERE01	McBSP1 Enhanced Transmit Channel Enable Register 0 Partition A/B
0290 0024	PCR1	McBSP1 Pin Control Register
0290 0028	RCERE11	McBSP1 Enhanced Receive Channel Enable Register 1 Partition C/D
0290 002C	XCERE11	McBSP1 Enhanced Transmit Channel Enable Register 1 Partition C/D
0290 0030	RCERE21	McBSP1 Enhanced Receive Channel Enable Register 2 Partition E/F
0290 0034	XCERE21	McBSP1 Enhanced Transmit Channel Enable Register 2 Partition E/F
0290 0038	RCERE31	McBSP1 Enhanced Receive Channel Enable Register 3 Partition G/H
0290 003C	XCERE31	McBSP1 Enhanced Transmit Channel Enable Register 3 Partition G/H
0290 0040 - 0293 FFFF	-	Reserved

4.7.10.2 McBSP Electrical Data/Timing

Table 4-61 McBSP Timing Requirements⁽¹⁾

(see Figure 4-51)

NO.				MIN	UNIT
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X ext	10P⁽²⁾	ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	0.5t_c(CKRX) - 1⁽²⁾	ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	9	ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR ext	1.3	ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	6	ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR ext	3	ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	8	ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR ext	0.9	ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	3	ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR ext	3.1	ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKR int	9	ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKR ext	1.3	ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKR int	6	ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKR ext	3	ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 4-62 Switching Characteristics for McBSP⁽¹⁾⁽²⁾⁽³⁾

(see Figure 4-51)

NO.	PARAMETER			MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input.⁽⁴⁾		1.4	10	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	10P⁽⁵⁾ ⁽⁶⁾ ⁽⁷⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	0.5t_c(CKRX) - 1		ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-2.1	3	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-1.7	3	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	1.7	9	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX Hi-Z following last data bit from CLKX high	CLKX int	-3.9	4	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	2	9	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-3.9	4	ns
			CLKX ext	2	9
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid applies ONLY when in data delay 0 (XDATDLY = 00b) mode	FSX int	-2.3 + D1⁽⁸⁾	5.6 + D2⁽⁸⁾	ns
14	t_d(FXH-DXV)		FSX ext	1.9 + D1⁽⁸⁾	9 + D2⁽⁸⁾	ns

(1) Over recommended operating conditions.

(2) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(3) Minimum delay times also represent minimum output hold times.

(4) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

(5) Minimum CLKR ÷ X cycle times must be met, even when CLKR ÷ X is generated by an internal clock source. Minimum CLKR ÷ X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements

(6) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(7) Use whichever value is greater

(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P

Figure 4-51 McBSP Timing

(A) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

(B) Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.

Table 4-63 Timing Requirements for FSR When GSYNC = 1

(see Figure 4-52)

NO.			MIN	MAX	UNIT
1	t_su(FRH-CKSH)	Setup time, FSR high before CLKS high	4		ns
2	t_h(CKSH-FRH)	Hold time, FSR high after CLKS high	4		ns

SM320C6457-HIREL FSR_Timing_When_GSYNC=1_6484.gif

Figure 4-52 FSR Timing When GSYNC = 1

Table 4-64 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾

(see Figure 4-53)

NO.			MASTER		SLAVE		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
4	t_su(DRV-CKXL)	Setup time, DR valid before CLKX low	12		2-12P		ns
5	t_h(CKXL-DRV)	Hold time, DR valid after CLKX low	4		5+24P		ns

(1) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

Table 4-65 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾

(see Figure 4-53)

NO.	PARAMETERS		MASTER		SLAVE		UNIT
NO.	PARAMETERS		MIN	MAX	MIN	MAX	UNIT
1	t_d(CKXL-FXH)	Delay time, FSX high after CLKX low	T-2	T+3			ns
2	t_d(FXL-CKXH)	Delay time, CLKX high after FSX low	L-3	L+3			ns
3	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	-2	4	12P+2.8	24P+17	ns
6	t_{dis(CKXL-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX low	L-2	L+3			ns
7	t_{dis(FXH-DXHZ)}	Disable time, DX high impedance following last data bit from FSX high			4P+3	12P+17	ns
8	td_(FXL-DXV)	Delay time, FSX low to DX valid			8P+1.8	18P+17	ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 6P if CLKSM = 1
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).

SM320C6457-HIREL SPI_Timing_M_or_S_CLKSTP=10b_CLKXP=0_6484.gif

Figure 4-53 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 0

Table 4-66 SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 1⁽¹⁾⁽²⁾

(see Figure 4-54)

NO.			MASTER		SLAVE		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
4	t_su(DRV-CKXH)	Setup time, DR valid before CLKX high	12		2-12P		ns
5	t_h(CKXH-DRV)	Hold time, DR valid after CLKX high	4		5+24P		ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 4-67 SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 1⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾

(see Figure 4-54)

NO.			MASTER		SLAVE		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	t_d(CKXH-FXH)	Delay time, FSX high after CLKX high	T-2	T+3			ns
2	t_d(FXL-CKXL)	Delay time, CLKX low after FSX low	H-3	H+3			ns
3	t_d(CKXL-DXV)	Delay time, CLKX low to DX valid	-2	4	12P + 2.8	24P + 17	ns
6	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	H-2	H+3			ns
7	t_{dis(FXH-DXHZ)}	Disable time, DX high impedance following last data bit from FSX high			4P+3	12P+17	ns
8	t_d(FXL-DXV)	Delay time, FSX low to DX valid			8P+2	18P+17	ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).

SM320C6457-HIREL SPI_Timing_M_or_S_CLKSTP=10b_CLKXP=1_6484.gif

Figure 4-54 SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 1

Table 4-68 SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 0⁽¹⁾⁽²⁾

(see Figure 4-55)

NO.			MASTER		SLAVE		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
4	t_su(DRV-CKXH)	Setup time, DR valid before CLKX high	12		2-12P		ns
5	t_h(CKXH-DRV)	Hold time, DR valid after CLKX high	4		5+24P		ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 4-69 SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 0⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾

(see Figure 4-55)

NO.			MASTER		SLAVE		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	t_d(CKXL-FXH)	Delay time, FSX high after CLKX low	L-2	L+3			ns
2	t_d(FXL-CKXH)	Delay time, CLKX high after FSX low	T-3	T+3			ns
3	t_d(CKXL-DXV)	Delay time, CLKX low to DX valid	-2	4	12P+2.8	24P+17	ns
6	t_{dis(CKXL-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX low	-2	4	12P+3	20P+17	ns
7	t_{dis(FXL-DXHZ)}	Disable time, DX high impedance following last data bit from FSX low	H-2	H+4	8P+2	18P+17	ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).

SM320C6457-HIREL SPI_Timing_M_or_S_CLKSTP=11b_CLKXP=0_6484.gif

Figure 4-55 SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 0

Table 4-70 SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾

(see Figure 4-56)

NO.			MASTER		SLAVE		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
4	t_su(DRV-CKXH)	Setup time, DR valid before CLKX high	12		2-12P		ns
5	t_h(CKXH-DRV)	Hold time, DR valid after CLKX high	4		5+24P		ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 4-71 SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾

(see Figure 4-56)

NO.			MASTER		SLAVE		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	t_d(CKXH-FXL)	Delay time, FSX low after CLKX high	H-2	H+3			ns
2	t_d(FXL-CKXL)	Delay time, CLKX low after FSX low	T-3	T+3			ns
3	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	-2	4	12P+2.8	24P+17	ns
6	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	-2	4	12P+3	20P+17	ns
7	t_{dis(FXL-DXHZ)}	Disable time, DX high impedance following last data bit from FSX low	L-2	L+4	8P+2	18P+17	ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 6P if CLKSM = 1
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even; H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).

SM320C6457-HIREL SPI_Timing_M_or_S_CLKSTP=11b_CLKXP=1_6484.gif

Figure 4-56 SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 1

4.7.11 Ethernet MAC (EMAC)

The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6457 DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

The EMAC control module is the main interface between the device core processor, the MDIO module, and the EMAC module. The relationship between these three components is shown in Figure 4-57. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC control module incorporates 8K-bytes of internal RAM to hold EMAC buffer descriptors.

SM320C6457-HIREL EMAC_MDIO_and_EMAC_Control_Modules_6484.gif

Figure 4-57 EMAC, MDIO, and EMAC Control Modules

For more detailed information on the EMAC/MDIO, see the TMS320C6457 DSP EMAC/MDIO Module Reference Guide (SPRUGK9).

4.7.11.1 EMAC Device-Specific Information

The EMAC module on the device supports Serial Gigabit Media Independent Interface (SGMII). The SGMII interface conforms to version 1.8 of the industry standard specification.

4.7.11.2 EMAC Peripheral Register Description(s)

The memory maps of the EMAC are shown in Table 4-72 through Table 4-77.

Table 4-72 Ethernet MAC (EMAC) Control Registers

HEX ADDRESS	ACRONYM	REGISTER NAME
02C8 0000	TXIDVER	Transmit Identification and Version Register
02C8 0004	TXCONTROL	Transmit Control Register
02C8 0008	TXTEARDOWN	Transmit Teardown register
02C8 000F	-	Reserved
02C8 0010	RXIDVER	Receive Identification and Version Register
02C8 0014	RXCONTROL	Receive Control Register
02C8 0018	RXTEARDOWN	Receive Teardown Register
02C8 001C	-	Reserved
02C8 0020 - 02C8 007C	-	Reserved
02C8 0080	TXINTSTATRAW	Transmit Interrupt Status (Unmasked) Register
02C8 0084	TXINTSTATMASKED	Transmit Interrupt Status (Masked) Register
02C8 0088	TXINTMASKSET	Transmit Interrupt Mask Set Register
02C8 008C	TXINTMASKCLEAR	Transmit Interrupt Mask Clear Register
02C8 0090	MACINVECTOR	MAC Input Vector Register
02C8 0094	MACEOIVECTOR	MAC End of Interrupt Vector Register
02C8 0098 - 02C8 019C	-	Reserved
02C8 00A0	RXINTSTATRAW	Receive Interrupt Status (Unmasked) Register
02C8 00A4	RXINTSTATMASKED	Receive Interrupt Status (Masked) Register
02C8 00A8	RXINTMASKSET	Receive Interrupt Mask Set Register
02C8 00AC	RXINTMASKCLEAR	Receive Interrupt Mask Clear Register
02C8 00B0	MACINTSTATRAW	MAC Interrupt Status (Unmasked) Register
02C8 00B4	MACINTSTATMASKED	MAC Interrupt Status (Masked) Register
02C8 00B8	MACINTMASKSET	MAC Interrupt Mask Set Register
02C8 00BC	MACINTMASKCLEAR	MAC Interrupt Mask Clear Register
02C8 00C0 - 02C8 00FC	-	Reserved
02C8 0100	RXMBPENABLE	Receive Multicast/Broadcast/Promiscuous Channel Enable Register
02C8 0104	RXUNICASTSET	Receive Unicast Enable Set Register
02C8 0108	RXUNICASTCLEAR	Receive Unicast Clear Register
02C8 010C	RXMAXLEN	Receive Maximum Length Register
02C8 0110	RXBUFFEROFFSET	Receive Buffer Offset Register
02C8 0114	RXFILTERLOWTHRESH	Receive Filter Low Priority Frame Threshold Register
02C8 0118 - 02C8 011C	-	Reserved
02C8 0120	RX0FLOWTHRESH	Receive Channel 0 Flow Control Threshold Register
02C8 0124	RX1FLOWTHRESH	Receive Channel 1 Flow Control Threshold Register
02C8 0128	RX2FLOWTHRESH	Receive Channel 2 Flow Control Threshold Register
02C8 012C	RX3FLOWTHRESH	Receive Channel 3 Flow Control Threshold Register
02C8 0130	RX4FLOWTHRESH	Receive Channel 4 Flow Control Threshold Register
02C8 0134	RX5FLOWTHRESH	Receive Channel 5 Flow Control Threshold Register
02C8 0138	RX6FLOWTHRESH	Receive Channel 6 Flow Control Threshold Register
02C8 013C	RX7FLOWTHRESH	Receive Channel 7 Flow Control Threshold Register
02C8 0140	RX0FREEBUFFER	Receive Channel 0 Free Buffer Count Register
02C8 0144	RX1FREEBUFFER	Receive Channel 1 Free Buffer Count Register
02C8 0148	RX2FREEBUFFER	Receive Channel 2 Free Buffer Count Register
02C8 014C	RX3FREEBUFFER	Receive Channel 3 Free Buffer Count Register
02C8 0150	RX4FREEBUFFER	Receive Channel 4 Free Buffer Count Register
02C8 0154	RX5FREEBUFFER	Receive Channel 5 Free Buffer Count Register
02C8 0158	RX6FREEBUFFER	Receive Channel 6 Free Buffer Count Register
02C8 015C	RX7FREEBUFFER	Receive Channel 7 Free Buffer Count Register
02C8 0160	MACCONTROL	MAC Control Register
02C8 0164	MACSTATUS	MAC Status Register
02C8 0168	EMCONTROL	Emulation Control Register
02C8 016C	FIFOCONTROL	FIFO Control Register
02C8 0170	MACCONFIG	MAC Configuration Register
02C8 074	SOFTRESET	Soft Reset Register
02C8 01D0	MACSRCADDRLO	MAC Source Address Low Bytes Register
02C8 01D4	MACSRCADDRHI	MAC Source Address High Bytes Register
02C8 01D8	MACHASH1	MAC Hash Address Register 1
02C8 01DC	MACHASH2	MAC Hash Address Register 2
02C8 01E0	BOFFTEST	Back Off Test Register
02C8 01E4	TPACETEST	Transmit Pacing Algorithm Test Register
02C8 01E8	RXPAUSE	Receive Pause Timer Register
02C8 01EC	TXPAUSE	Transmit Pause Timer Register
02C8 0300 - 02C8 03FC	-	Reserved
02C8 0400 - 02C8 04FC	-	Reserved
02C8 0500	MACADDRLO	MAC Address Low Bytes Register (used in Receive Address Matching)
02C8 0504	MACADDRHI	MAC Address High Bytes Register (used in Receive Address Matching)
02C8 0508	MACINDEX	MAC Index Register
02C8 050C - 02C8 05FC	-	Reserved
02C8 0600	TX0HDP	Transmit Channel 0 DMA Head Descriptor Pointer Register
02C8 0604	TX1HDP	Transmit Channel 1 DMA Head Descriptor Pointer Register
02C8 0608	TX2HDP	Transmit Channel 2 DMA Head Descriptor Pointer Register
02C8 060C	TX3HDP	Transmit Channel 3 DMA Head Descriptor Pointer Register
02C8 0610	TX4HDP	Transmit Channel 4 DMA Head Descriptor Pointer Register
02C8 0614	TX5HDP	Transmit Channel 5 DMA Head Descriptor Pointer Register
02C8 0618	TX6HDP	Transmit Channel 6 DMA Head Descriptor Pointer Register
02C8 061C	TX7HDP	Transmit Channel 7 DMA Head Descriptor Pointer Register
02C8 0620	RX0HDP	Receive Channel 0 DMA Head Descriptor Pointer Register
02C8 0624	RX1HDP	Receive t Channel 1 DMA Head Descriptor Pointer Register
02C8 0628	RX2HDP	Receive Channel 2 DMA Head Descriptor Pointer Register
02C8 062C	RX3HDP	Receive t Channel 3 DMA Head Descriptor Pointer Register
02C8 0630	RX4HDP	Receive Channel 4 DMA Head Descriptor Pointer Register
02C8 0634	RX5HDP	Receive t Channel 5 DMA Head Descriptor Pointer Register
02C8 0638	RX6HDP	Receive Channel 6 DMA Head Descriptor Pointer Register
02C8 063C	RX7HDP	Receive t Channel 7 DMA Head Descriptor Pointer Register
02C8 0640	TX0CP	Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register
02C8 0644	TX1CP	Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register
02C8 0648	TX2CP	Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register
02C8 064C	TX3CP	Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register
02C8 0650	TX4CP	Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register
02C8 0654	TX5CP	Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register
02C8 0658	TX6CP	Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register
02C8 065C	TX7CP	Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register
02C8 0660	RX0CP	Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register
02C8 0664	RX1CP	Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register
02C8 0668	RX2CP	Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register
02C8 066C	RX3CP	Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register
02C8 0670	RX4CP	Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register
02C8 0674	RX5CP	Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register
02C8 0678	RX6CP	Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register
02C8 067C	RX7CP	Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register
02C8 0680 - 02C8 06FC	-	Reserved
02C8 0700 - 02C8 077C	-	Reserved
02C8 0780 - 02C8 0FFF	-	Reserved

Table 4-73 EMAC Statistics Registers

HEX ADDRESS	ACRONYM	REGISTER NAME
02C8 0200	RXGOODFRAMES	Good Receive Frames Register
02C8 0204	RXBCASTFRAMES	Broadcast Receive Frames Register (Total number of Good Broadcast Frames Receive)
02C8 0208	RXMCASTFRAMES	Multicast Receive Frames Register (Total number of Good Multicast Frames Received)
02C8 020C	RXPAUSEFRAMES	Pause Receive Frames Register
02C8 0210	RXCRCERRORS	Receive CRC Errors Register (Total number of Frames Received with CRC Errors)
02C8 0214	RXALIGNCODEERRORS	Receive Alignment/Code Errors register (Total number of frames received with alignment/code errors)
02C8 0218	RXOVERSIZED	Receive Oversized Frames Register (Total number of Oversized Frames Received)
02C8 021C	RXJABBER	Receive Jabber Frames Register (Total number of Jabber Frames Received)
02C8 0220	RXUNDERSIZED	Receive Undersized Frames Register (Total number of Undersized Frames Received)
02C8 0224	RXFRAGMENTS	Receive Frame Fragments Register
02C8 0228	RXFILTERED	Filtered Receive Frames Register
02C8 022C	RXQOSFILTERERED	Received QOS Filtered Frames Register
02C8 0230	RXOCTETS	Receive Octet Frames Register (Total number of Received Bytes in Good Frames)
02C8 0234	TXGOODFRAMES	Good Transmit Frames Register (Total number of Good Frames Transmitted)
02C8 0238	TXBCASTFRAMES	Broadcast Transmit Frames Register
02C8 023C	TXMCASTFRAMES	Multicast Transmit Frames Register
02C8 0240	TXPAUSEFRAMES	Pause Transmit Frames Register
02C8 0244	TXDEFERED	Deferred Transmit Frames Register
02C8 0248	TXCOLLISION	Transmit Collision Frames Register
02C8 024C	TXSINGLECOLL	Transmit Single Collision Frames Register
02C8 0250	TXMULTICOLL	Transmit Multiple Collision Frames Register
02C8 0254	TXEXCESSIVECOLL	Transmit Excessive Collision Frames Register
02C8 0258	TXLATECOLL	Transmit Late Collision Frames Register
02C8 025C	TXUNDERRUN	Transmit Under Run Error Register
02C8 0260	TXCARRIERSENSE	Transmit Carrier Sense Errors Register
02C8 0264	TXOCTETS	Transmit Octet Frames Register
02C8 0268	FRAME64	Transmit and Receive 64 Octet Frames Register
02C8 026C	FRAME65T127	Transmit and Receive 65 to 127 Octet Frames Register
02C8 0270	FRAME128T255	Transmit and Receive 128 to 255 Octet Frames Register
02C8 0274	FRAME256T511	Transmit and Receive 256 to 511 Octet Frames Register
02C8 0278	FRAME512T1023	Transmit and Receive 512 to 1023 Octet Frames Register
02C8 027C	FRAME1024TUP	Transmit and Receive 1024 to 1518 Octet Frames Register
02C8 0280	NETOCTETS	Network Octet Frames Register
02C8 0284	RXSOFOVERRUNS	Receive FIFO or DMA Start of Frame Overruns Register
02C8 0288	RXMOFOVERRUNS	Receive FIFO or DMA Middle of Frame Overruns Register
02C8 028C	RXDMAOVERRUNS	Receive DMA Start of Frame and Middle of Frame Overruns Register
02C8 0290 - 02C8 02FC	-	Reserved

Table 4-74 EMAC Descriptor Memory

HEX ADDRESS	ACRONYM	REGISTER NAME
02E0 0000 - 02E0 3FFF	-	EMAC Descriptor Memory

Table 4-75 SGMII Control Registers

HEX ADDRESS	ACRONYM	REGISTER NAME
02C4 0000	IDVER	Identification and Version register
02C4 0004	SOFT_RESET	Software Reset Register
02C4 0010	CONTROL	Control Register
02C4 0014	STATUS	Status Register
02C4 0018	MR_ADV_ABILITY	Advertised Ability Register
02C4 001C	-	Reserved
02C4 0020	MR_LP_ADV_ABILITY	Link Partner Advertised Ability Register
02C4 0024	-	Reserved
02C4 0030	TX_CFG	Transmit Configuration Register
02C4 0034	RX_CFG	Receive Configuration Register
02C4 0038	AUX_CFG	Auxiliary Configuration Register
02C4 0040 - 02C4 0048	-	Reserved

Table 4-76 EMIC Control Registers

HEX ADDRESS	ACRONYM	REGISTER NAME
02C8 1000	IDVER	Identification and Version register
02C8 1004	SOFT_RESET	Software Reset Register
02C8 1008	EM_CONTROL	Emulation Control Register
02C8 100C	INT_CONTROL	Interrupt Control Register
02C8 1010	C_RX_THRESH_EN	Receive Threshold Interrupt Enable Register
02C8 1014	C_RX_EN	Receive Interrupt Enable Register
02C8 1018	C_TX_EN	Transmit Interrupt Enable Register
02C8 101C	C_MISC_EN	Misc Interrupt Enable Register
02C8 1040	C_RX_THRESH_STAT	Receive Threshold Masked Interrupt Status Register
02C8 1044	C_RX_STAT	Receive Interrupt Masked Interrupt Status Register
02C8 1048	C_TX_STAT	Transmit Interrupt Masked Interrupt Status Register
02C8 104C	C_MISC_STAT	Misc Interrupt Masked Interrupt Status Register
02C8 1070	C_RX_IMAX	Receive Interrupts Per Millisecond
02C8 1074	C_TX_IMAX	Transmit Interrupts Per Millisecond

4.7.11.3 EMAC Electrical Data/Timing (SGMII)

The TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide application report (SPRAAV7) specifies a complete EMAC and SGMII interface solutions for the C6457 as well as a list of compatible EMAC and SGMII devices. TI has performed the simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

4.7.12 Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor.

The EMAC control module is the main interface between the device core processor, the MDIO module, and the EMAC module. The relationship between these three components is shown in Figure 4-57.

For more detailed information on the EMAC/MDIO, see the TMS320C6457 DSP EMAC/MDIO Module Reference Guide (SPRUGK9).

4.7.12.1 MDIO Peripheral Register Description(s)

The memory map of the MDIO is shown in Table 4-77.

Table 4-77 MDIO Registers

HEX ADDRESS	ACRONYM	REGISTER NAME
02C8 1800	VERSION	MDIO Version Register
02C8 1804	CONTROL	MDIO Control Register
02C8 1808	ALIVE	MDIO PHY Alive Status Register
02C8 180C	LINK	MDIO PHY Link Status Register
02C8 1810	LINKINTRAW	MDIO link Status Change Interrupt (unmasked) Register
02C8 1814	LINKINTMASKED	MDIO link Status Change Interrupt (masked) Register
02C8 1818 - 02C8 181C	-	Reserved
02C8 1820	USERINTRAW	MDIO User Command Complete Interrupt (Unmasked) Register
02C8 1824	USERINTMASKED	MDIO User Command Complete Interrupt (Masked) Register
02C8 1828	USERINTMASKSET	MDIO User Command Complete Interrupt Mask Set Register
02C8 182C	USERINTMASKCLEAR	MDIO User Command Complete Interrupt Mask Clear Register
02C8 1830 - 02C8 187C	-	Reserved
02C8 1880	USERACCESS0	MDIO User Access Register 0
02C8 1884	USERPHYSEL0	MDIO User PHY Select Register 0
02C8 1888	USERACCESS1	MDIO User Access Register 1
02C8 188C	USERPHYSEL1	MDIO User PHY Select Register 1
02C8 1890 - 02C8 1FFF	-	Reserved

4.7.12.2 MDIO Electrical Data/Timing

Table 4-78 MDIO Input Timing Requirements

(see Figure 4-58)

NO.			MIN	MAX	UNIT
1	t_c(MDCLK)	Cycle time, MDCLK	400		ns
2a	t_w(MDCLKH)	Pulse duration, MDCLK high	180		ns
2b	t_w(MDCLKL)	Pulse duration, MDCLK low	180		ns
3	t_t(MDCLK)	Transition time, MDCLK		5	ns
4	t_{su(MDIO-MDCLKH)}	Setup time, MDIO data input valid before MDCLK high	10		ns
5	t_{h(MDCLKH-MDIO)}	Hold time, MDIO data input valid after MDCLK high	10		ns

SM320C6457-HIREL MDIO_Input_Timing_6484.gif

Figure 4-58 MDIO Input Timing

Table 4-79 MDIO Output Switching Characteristics⁽¹⁾

(see Figure 4-59)

NO.	PARAMETER		MIN	MAX	UNIT
7	t_{d(MDCLKL-MDIO)}	Delay time, MDCLK low to MDIO data output valid	100		ns

(1) Over recommended operating conditions.

SM320C6457-HIREL MDIO_Output_Timing_6484.gif

Figure 4-59 MDIO Output Timing

4.7.13 Timers

The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDMA3 channel controller.

4.7.13.1 Timers Device-Specific Information

The C6457 device has two general-purpose timers, Timer0 and Timer1, each of which can be configured as a general-purpose timer or as a watchdog timer. When configured as a general-purpose timer, each timer can be programmed as a 64-bit timer or as two separate 32-bit timers.

Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The high counter does not have any external device pins.

4.7.13.1.1 Timer Watchdog Select

As mentioned previously, the timers can operate in watchdog mode. When in watchdog mode, the event output from Timer1 can optionally reset the CPU. In order for the event to trigger the reset when this operation is desired, the Timer1 watchdog reset selection register (WDRSTSEL) should be set to 1. The WDRSTSEL register is shown in Figure 4-60 and described in Table 4-80.

Figure 4-60 Timer1 Watchdog Reset Selection Register (WDRSTSEL) (Address - 0288 0920h)

Reserved

R- 0000 0000 0000 0000 0000 0000 0000 000

Reserved

WDRSTSEL

R- 0000 0000 0000 0000 0000 0000 0000 000

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-80 Timer1 Watchdog Reset Selection Register (WDRSTSEL) Field Descriptions

Bit	Acronym	Description
31:1	Reserved	Reserved.
0	WRDSTSEL	Reset Select for Watchdog Timer1 0 = TOUT1L does not cause a reset to the C64x+ megamodule (default) 1 = TOUT1L causes a reset to the C64x+ megamodule

4.7.13.2 Timers Peripheral Register Description(s)

Table 4-81 Timer 0 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
0294 0000	-	Reserved
0294 0004	EMUMGT_CLKSPD0	Timer 0 Emulation Management/Clock Speed Register
0294 0008	-	Reserved
0294 000C	-	Reserved
0294 0010	CNTLO0	Timer 0 Counter Register Low
0294 0014	CNTHI0	Timer 0 Counter Register High
0294 0018	PRDLO0	Timer 0 Period Register Low
0294 001C	PRDHI0	Timer 0 Period Register High
0294 0020	TCR0	Timer 0 Control Register
0294 0024	TGCR0	Timer 0 Global Control Register
0294 0028	WDTCR0	Timer 0 Watchdog Timer Control Register
0294 002C	-	Reserved
0294 0030	-	Reserved
0294 0034 - 0297 FFFF	-	Reserved

Table 4-82 Timer 1 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
0298 0000	-	Reserved
0298 0004	EMUMGT_CLKSPD1	Timer 1 Emulation Management/Clock Speed Register
0298 0008	-	Reserved
0298 000C	-	Reserved
0298 0010	CNTLO1	Timer 1 Counter Register Low
0298 0014	CNTHI1	Timer 1 Counter Register High
0298 0018	PRDLO1	Timer 1 Period Register Low
0298 001C	PRDHI1	Timer 1 Period Register High
0298 0020	TCR1	Timer 1 Control Register
0298 0024	TGCR1	Timer 1 Global Control Register
0298 0028	WDTCR1	Timer 1 Watchdog Timer Control Register
0298 002C	-	Reserved
0298 0030	-	Reserved
0298 0034 - 0299 FFFF	-	Reserved

4.7.13.3 Timers Electrical Data/Timing

The below tables and figures describe the timing requirements and switching characteristics of both the Timer0 and Timer1 peripherals.

Table 4-83 Timer Input Timing Requirements⁽¹⁾

(see Figure 4-61)

NO.			MIN	MAX	UNIT
1	t_w(TIMIH)	Pulse duration, TIMI high	12C		ns
2	t_w(TIMIL)	Pulse duration, TIMI low	12C		ns

(1) If CORECLKSEL = 0, C = 1/CORECLK(NIP) frequency in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency in ns.

Table 4-84 Timer Output Switching Characteristics⁽¹⁾⁽²⁾

(see Figure 4-61)

NO.	PARAMETER		MIN	MAX	UNIT
3	t_w(TIMOH)	Pulse duration, TIMO high	12C - 3		ns
4	t_w(TIMOL)	Pulse duration, TIMO low	12C - 3		ns

(1) Over recommended operating conditions.

(2) If CORECLKSEL = 0, C = 1/CORECLK(NIP) frequency in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency in ns.

Figure 4-61 Timer Timing

4.7.14 Enhanced Viterbi-Decoder Coprocessor (VCP2)

4.7.14.1 VCP2 Device-Specific Information

The C6457 device has a high-performance embedded Viterbi-Decoder Coprocessor (VCP2) that significantly speeds up channel-decoding operations on-chip. The VCP2, operating at CPU clock divided-by-3, can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP2 and the CPU are carried out through the EDMA3 controller.

The VCP2 supports:

Unlimited frame sizes
Code rates 3/4, 1/2, 1/3, 1/4, and 1/5
Constraint lengths 5, 6, 7, 8, and 9
Programmable encoder polynomials
Programmable reliability and convergence lengths
Hard and soft decoded decisions
Tail and convergent modes
Yamamoto logic
Tail biting logic
Various input and output FIFO lengths

For more detailed information on the VCP2, see the TMS320C6457 DSP Viterbi-Decoder Coprocessor 2 (VCP2) Reference Guide (SPRUGK0).

4.7.14.2 VCP2 Peripheral Register Description

Table 4-85 VCP2 Registers

EDMA BUS HEX ADDRESS RANGE	CONFIGURATION BUS HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
5800 0000	-	VCPIC0	VCP2 Input Configuration Register 0
5800 0004	-	VCPIC1	VCP2 Input Configuration Register 1
5800 0008	-	VCPIC2	VCP2 Input Configuration Register 2
5800 000C	-	VCPIC3	VCP2 Input Configuration Register 3
5800 0010	-	VCPIC4	VCP2 Input Configuration Register 4
5800 0014	-	VCPIC5	VCP2 Input Configuration Register 5
5800 0018 - 5800 0044		-	Reserved
5800 0048	-	VCPOUT0	VCP2 Output Register 0
5800 004C	-	VCPOUT1	VCP2 Output Register 1
5800 0050 - 5800 007C		-	Reserved
5800 0080	N/A	VCPWBM	VCP2 Branch Metrics Write FIFO Register
5800 0084 - 5800 009C		-	Reserved
5800 00C0	N/A	VCPRDECS	VCP2 Decisions Read FIFO Register
N/A	02B8 0000	VCPPID	VCP2 Peripheral ID Register
N/A	02B8 0018	VCPEXE	VCP2 Execution Register
N/A	02B8 0020	VCPEND	VCP2 Endian Mode Register
N/A	02B8 0040	VCPSTAT0	VCP2 Status Register 0
N/A	02B8 0044	VCPSTAT1	VCP2 Status Register 1
N/A	02B8 0050	VCPERR	VCP2 Error Register
-	-	-	Reserved
N/A	02B8 0060	VCPEMU	VCP2 Emulation Control Register
N/A	02B8 0064 - 02B9 FFFF	-	Reserved
5800 1000	-	BM	Branch Metrics
5800 2000	-	SM	State Metric
5800 3000	-	TBHD	Traceback Hard Decision
5800 6000	-	TBSD	Traceback Soft Decision
5800 F000	-	IO	Decoded Bits

4.7.15 Enhanced Turbo Decoder Coprocessor (TCP2)

4.7.15.1 TCP2 Device-Specific Information

The C6457 device has two high-performance embedded Turbo-Decoder Coprocessors (TCP2_A and TCP2_B) that significantly speed up channel-decoding operations on-chip. Each TCP2, operating at CPU clock divided-by-3, can decode up to fifty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 6 iterations). The TCP2 implements the max * log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the TCP2 and the CPU are carried out through the EDMA3 controller.

Each TCP2 supports:

Parallel concatenated convolutional turbo decoding using the MAP algorithm
All turbo code rates greater than or equal to 1/5
3GPP and CDMA2000 turbo encoder trellis
3GPP and CDMA2000 block sizes in standalone mode
Larger block sizes in shared processing mode
Both max log MAP and log MAP decoding
Sliding windows algorithm with variable reliability and prolog lengths
The prolog reduction algorithm
Execution of a minimum and maximum number of iterations
The SNR stopping criteria algorithm
The CRC stopping criteria algorithm

For more detailed information on the TCP2, see the TMS320C6457 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide (SPRUGK1).

Table 4-86 TCP2_A Registers

EDMA BUS HEX ADDRESS RANGE	CONFIGURATION BUS HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
5000 0000	-	TCPIC0	TCP2 Input Configuration Register 0
5000 0004	-	TCPIC1	TCP2 Input Configuration Register 1
5000 0008	-	TCPIC2	TCP2 Input Configuration Register 2
5000 000C	-	TCPIC3	TCP2 Input Configuration Register 3
5000 0010	-	TCPIC4	TCP2 Input Configuration Register 4
5000 0014	-	TCPIC5	TCP2 Input Configuration Register 5
5000 0018	-	TCPIC6	TCP2 Input Configuration Register 6
5000 001C	-	TCPIC7	TCP2 Input Configuration Register 7
5000 0020	-	TCPIC8	TCP2 Input Configuration Register 8
5000 0024	-	TCPIC9	TCP2 Input Configuration Register 9
5000 0028	-	TCPIC10	TCP2 Input Configuration Register 10
5000 002C	-	TCPIC11	TCP2 Input Configuration Register 11
5000 0030	-	TCPIC12	TCP2 Input Configuration Register 12
5000 0034	-	TCPIC13	TCP2 Input Configuration Register 13
5000 0038	-	TCPIC14	TCP2 Input Configuration Register 14
5000 003C	-	TCPIC15	TCP2 Input Configuration Register 15
5000 0040	-	TCPOUT0	TCP2 Output Parameters Register 0
5000 0044	-	TCPOUT1	TCP2 Output Parameters Register 1
5000 0048	-	TCPOUT2	TCP2 Output Parameters Register 2
5001 0000	N/A	X0	TCP2 Data/Sys and Parity Memory
5003 0000	N/A	W0	TCP2 Extrinsic Mem 0
5004 0000	N/A	W1	TCP2 Extrinsic Mem 1
5005 0000	N/A	I0	TCP2 Interleaver Memory
5006 0000	N/A	O0	TCP2 Output/Decision Memory
5007 0000	N/A	S0	TCP2 Scratch Pad Memory
5008 0000	N/A	T0	TCP2 Beta State Memory
5009 0000	N/A	C0	TCP2 CRC Memory
500A 0000	N/A	B0	TCP2 Beta Prolog Memory
500B 0000	N/A	A0	TCP2 Alpha Prolog Memory
	02BA 0000	TCPPID	TCP2 Peripheral Identification Register
N/A	02BA 004C	TCPEXE	TCP2 Execute Register
N/A	02BA 0050	TCPEND	TCP2 Endianness Register
N/A	02BA 0060	TCPERR	TCP2 Error Register
N/A	02BA 0068	TCPSTAT	TCP2 Status Register
N/A	02BA 0070	TCPEMU	TCP2 Emulation Register
N/A	02BA 0074 - 02BA 00FF	-	Reserved

Table 4-87 TCP2_B Registers

EDMA BUS HEX ADDRESS RANGE	CONFIGURATION BUS HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
5010 0000	-	TCPIC0	TCP2 Input Configuration Register 0
5010 0004	-	TCPIC1	TCP2 Input Configuration Register 1
5010 0008	-	TCPIC2	TCP2 Input Configuration Register 2
5010 000C	-	TCPIC3	TCP2 Input Configuration Register 3
5010 0010	-	TCPIC4	TCP2 Input Configuration Register 4
5010 0014	-	TCPIC5	TCP2 Input Configuration Register 5
5010 0018	-	TCPIC6	TCP2 Input Configuration Register 6
5010 001C	-	TCPIC7	TCP2 Input Configuration Register 7
5010 0020	-	TCPIC8	TCP2 Input Configuration Register 8
5010 0024	-	TCPIC9	TCP2 Input Configuration Register 9
5010 0028	-	TCPIC10	TCP2 Input Configuration Register 10
5010 002C	-	TCPIC11	TCP2 Input Configuration Register 11
5010 0030	-	TCPIC12	TCP2 Input Configuration Register 12
5010 0034	-	TCPIC13	TCP2 Input Configuration Register 13
5010 0038	-	TCPIC14	TCP2 Input Configuration Register 14
5010 003C	-	TCPIC15	TCP2 Input Configuration Register 15
5010 0040	-	TCPOUT0	TCP2 Output Parameters Register 0
5010 0044	-	TCPOUT1	TCP2 Output Parameters Register 1
5010 0048	-	TCPOUT2	TCP2 Output Parameters Register 2
5011 0000	N/A	X0	TCP2 Data/Sys and Parity Memory
5013 0000	N/A	W0	TCP2 Extrinsic Mem 0
5014 0000	N/A	W1	TCP2 Extrinsic Mem 1
5015 0000	N/A	I0	TCP2 Interleaver Memory
5016 0000	N/A	O0	TCP2 Output/Decision Memory
5017 0000	N/A	S0	TCP2 Scratch Pad Memory
5018 0000	N/A	T0	TCP2 Beta State Memory
5019 0000	N/A	C0	TCP2 CRC Memory
501A 0000	N/A	B0	TCP2 Beta Prolog Memory
501B 0000	N/A	A0	TCP2 Alpha Prolog Memory
	02BA 0100	TCPPID	TCP2 Peripheral Identification Register
N/A	02BA 014C	TCPEXE	TCP2 Execute Register
N/A	02BA 0150	TCPEND	TCP2 Endianness Register
N/A	02BA 0160	TCPERR	TCP2 Error Register
N/A	02BA 0168	TCPSTAT	TCP2 Status Register
N/A	02BA 0170	TCPEMU	TCP2 Emulation Register
N/A	02BA 0174 - 02BB FFFF	-	Reserved

4.7.16 UTOPIA

4.7.16.1 UTOPIA Device-Specific Information

The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8-Bit Slave-only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is serviced directly by the EDMA3 controller. The UTOPIA peripheral contains two, two-cell FIFOs, one for transmit and one for receive, with which to buffer up data sent/received across the pins. There is a transmit and a receive event to the EDMA3 channel controller to enable servicing.

For more detailed information on the UTOPIA peripheral, see the TMS320C6457 DSP Universal Test and Operations PHY Interface for ATM 2 (UTOPIA2) (SPRUGL1).

4.7.16.2 UTOPIA Peripheral Register Description(s)

Table 4-88 UTOPIA Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02B4 0000	UCR	UTOPIA Control Register
02B4 0004	-	Reserved
02B4 0008	-	Reserved
02B4 000C	-	Reserved
02B4 0010	-	Reserved
02B4 0014	CDR	Clock Detect Register
02B4 0018	EIER	Error Interrupt Enable Register
02B4 001C	EIPR	Error Interrupt Pending Register
02B4 0020 - 02B4 01FF	-	Reserved
02B4 0200 - 02B7 FFFF	-	Reserved

Table 4-89 UTOPIA Data Queues (Receive and Transmit) Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
3D00 0000 - 3D00 007F	URQ	UTOPIA Receive (RX) Data Queue
3D00 0080 - 3D00 03FF	-	Reserved
3D00 0400 - 3D00 047F	UXQ	UTOPIA Transmit (TX) Data Queue
3D00 0480 - 3D00 07FF	-	Reserved

4.7.16.3 UTOPIA Electrical Data/Timing

Table 4-90 UXCLK Timing Requirements⁽¹⁾

(see Figure 4-62)

NO.			MIN	MAX	UNIT
1	t_c(UXCK)	Cycle time, UXCLK	20		ns
2	t_w(UXCKH)	Pulse duration, UXCLK high	0.4t_c(UXCK)	0.6t_c(UXCK)	ns
3	t_w(UXCKL)	Pulse duration, UXCLK low	0.4t_c(UXCK)	0.6t_c(UXCK)	ns
4	t_t(UXCK)	Transition time, UXCLK		2	ns

(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

Figure 4-62 UXCLK Timing

Table 4-91 URCLK Timing Requirements⁽¹⁾

(see Figure 4-63)

NO.			MIN	MAX	UNIT
1	t_c(URCK)	Cycle time, URCLK	20		ns
2	t_w(URCKH)	Pulse duration, URCLK high	0.4t_c(URCK)	0.6t_c(URCK)	ns
3	t_w(URCKL)	Pulse duration, URCLK low	0.4t_c(URCK)	0.6t_c(URCK)	ns
4	t_t(URCK)	Transition time, URCLK		2	ns

(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

Figure 4-63 URCLK Timing

Table 4-92 UTOPIA Slave Transmit Timing Requirements

(see Figure 4-64)

NO.			MIN	UNIT
2	t_{su(UXAV-UXCH)}	Setup time, UXADDR valid before UXCLK high	4	ns
3	t_h(UXCH-UXAV)	Hold time, UXADDR valid after UXCLK high	1	ns
8	t_{su(UXENBL-UXCH)}	Setup time, UXENB low before UXCLK high	4	ns
9	t_{h(UXCH-UXENBL)}	Hold time, UXENB low after UXCLK high	1	ns

Table 4-93 UTOPIA Slave Transmit Cycles Switching Characteristics⁽¹⁾

(see Figure 4-64)

No.	Parameter		Min	Max	Unit
1	t_d(UXCH-UXDV)	Delay time, UXCLK high to UXDATA valid	2	12	ns
4	t_{d(UXCH-UXCLAV)}	Delay time, UXCLK high to UXCLAV driven active value	2	12	ns
5	t_{d(UXCH-UXCLAVL)}	Delay time, UXCLK high to UXCLAV driven inactive low	2	12	ns
6	t_{d(UXCH-UXCLAVHZ)}	Delay time, UXCLK high to UXCLAV going Hi-Z	9	18.5	ns
7	t_{w(UXCLAVL-UXCLAVHZ)}	Pulse duration (low), UXCLAV low to UXCLAV Hi-Z	2		ns
10	t_d(UXCH-UXSV)	Delay time, UXCLK high to UXSOC valid	2	12	ns

(1) Over recommended operating conditions.

SM320C6457-HIREL UTOPIA_Slave_Transmit_Timing_6484.gif

Figure 4-64 UTOPIA Slave Transmit Timing^(A)

(A) The UTOPIA slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals).

Table 4-94 UTOPIA Slave Receive Timing Requirements

(see Figure 4-65)

NO.			MIN	UNIT
1	t_{su(URDV-URCH)}	Setup time, URDATA valid before URCLK high	4	ns
2	t_h(URCH-URDV)	Hold time, URDATA valid after URCLK high	1	ns
3	t_{su(URAV-URCH)}	Setup time, URADDR valid before URCLK high	4	ns
4	t_h(URCH-URAV)	Hold time, URADDR valid after URCLK high	1	ns
9	t_{su(URENBL-URCH)}	Setup time, URENB low before URCLK high	4	ns
10	t_{h(URCH-URENBL)}	Hold time, URENB low after URCLK high	1	ns
11	t_{su(URSH-URCH)}	Setup time, URSOC high before URCLK high	4	ns
12	t_h(URCH-URSH)	Hold time, URSOC high after URCLK high	1	ns

Table 4-95 Switching Characteristics for UTOPIA Slave Receive Cycles⁽¹⁾

(see Figure 4-65)

NO.	PARAMETER		MIN	MAX	UNIT
5	t_{d(URCH-URCLAV)}	Delay time, URCLK high to URCLAV driven active value	3	12	ns
6	t_{d(URCH-URCLAVL)}	Delay time, URCLK high to URCLAV driven inactive low	3	12	ns
7	t_{d(URCH-URCLAVHZ)}	Delay time, URCLK high to URCLAV going Hi-Z	9	18.5	ns
8	t_{w(URCLAVL-URCLAVHZ)}	Pulse duration (low), URCLAV low to URCLAV Hi-Z	3		ns

(1) Over recommended operating conditions.

SM320C6457-HIREL UTOPIA_Slave_Receive_Timing_6484.gif

Figure 4-65 UTOPIA Slave Receive Timing^(A)

(A) The UTOPIA slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC signals).

4.7.17 Serial RapidIO (SRIO) Port

The SRIO port on the C6457 device is a high-performance, low pin-count interconnect aimed for embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous interconnect environment, providing even more connectivity and control among the components. RapidIO is based on the memory and device addressing concepts of processor buses where the transaction processing is managed completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency, reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless interfaces. The RapidIO interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per second (Gbps) bidirectional links.

The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the parallel-to-serial/serial-to-parallel converters.

The C6457 device supports four 1× or one 4× Serial RapidIO links. The RapidIO interface should be designed to operate at a data rate of 3.125 Gbps per differential pair. This equals 12.5 raw GBaud/s for the 4× RapidIO port, or approximately 9 Gbps data throughput rate.

4.7.17.1 Serial RapidIO Device-Specific Information

The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as EMIFA, HPI, and McBSP. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models.

For the C6457 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing two DSPs connected via a 4× SRIO link directly to the user. TI has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system solution is documented in the TMS320TCI6484 and TMS320C6457 SerDes Implementation Guidelines application report (SPRAAY1).

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

The Serial RapidIO peripheral is a master peripheral in the C6457 DSP. It conforms to the RapidIO™ Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.

4.7.17.2 Serial RapidIO Peripheral Register Description(s)

Table 4-96 RapidIO Control Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02D0 0000	RIO_PID	Peripheral Identification Register
02D0 0004	RIO_PCR	Peripheral Control Register
02D0 0008 - 02D0 001C	-	Reserved
02D0 0020	RIO_PER_SET_CNTL0	Peripheral Settings Control Register 0
02D0 0024	RIO_PER_SET_CNTL1	Peripheral Settings Control Register 1
02D0 0028 - 02D0 002C	-	Reserved
02D0 0030	RIO_GBL_EN	Peripheral Global Enable Register
02D0 0034	RIO_GBL_EN_STAT	Peripheral Global Enable Status
02D0 0038	RIO_BLK0_EN	Block Enable 0
02D0 003C	RIO_BLK0_EN_STAT	Block Enable Status 0
02D0 0040	RIO_BLK1_EN	Block Enable 1
02D0 0044	RIO_BLK1_EN_STAT	Block Enable Status 1
02D0 0048	BLK2_EN	Block Enable 2
02D0 004C	BLK2_EN_STAT	Block Enable Status 2
02D0 0050	BLK3_EN	Block Enable 3
02D0 0054	BLK3_EN_STAT	Block Enable Status 3
02D0 0058	BLK4_EN	Block Enable 4
02D0 005C	BLK4_EN_STAT	Block Enable Status 4
02D0 0060	BLK5_EN	Block Enable 5
02D0 0064	BLK5_EN_STAT	Block Enable Status 5
02D0 0068	BLK6_EN	Block Enable 6
02D0 006C	BLK6_EN_STAT	Block Enable Status 6
02D0 0070	BLK7_EN	Block Enable 7
02D0 0074	BLK7_EN_STAT	Block Enable Status 7
02D0 0078	BLK8_EN	Block Enable 8
02D0 007C	BLK8_EN_STAT	Block Enable Status 8
02D0 0080	DEVICEID_REG1	RapidIO DEVICEID1 Register
02D0 0084	DEVICEID_REG2	RapidIO DEVICEID2 Register
02D0 0088	DEVICEID_REG3	RapidIO DEVICEID3 Register
02D0 008C	DEVICEID_REG4	RapidIO DEVICEID4 Register
02D0 0090	PF_16B_CNTL0	Packet Forwarding Register 0 for 16-bit Device IDs
02D0 0094	PF_8B_CNTL0	Packet Forwarding Register 0 for 8-bit Device IDs
02D0 0098	PF_16B_CNTL1	Packet Forwarding Register 1 for 16-bit Device IDs
02D0 009C	PF_8B_CNTL1	Packet Forwarding Register 1 for 8-bit Device IDs
02D0 00A0	PF_16B_CNTL2	Packet Forwarding Register 2 for 16-bit Device IDs
02D0 00A4	PF_8B_CNTL2	Packet Forwarding Register 2 for 8-bit Device IDs
02D0 00A8	PF_16B_CNTL3	Packet Forwarding Register 3 for 16-bit Device IDs
02D0 00AC	PF_8B_CNTL3	Packet Forwarding Register 3 for 8-bit Device IDs
02D0 00B0 - 02D0 00FC	-	Reserved
02D0 0100	SERDES_CFGRX0_CNTL	SerDes Receive Channel Configuration Register 0
02D0 0104	SERDES_CFGRX1_CNTL	SerDes Receive Channel Configuration Register 1
02D0 0108	SERDES_CFGRX2_CNTL	SerDes Receive Channel Configuration Register 2
02D0 010C	SERDES_CFGRX3_CNTL	SerDes Receive Channel Configuration Register 3
02D0 0110	SERDES_CFGTX0_CNTL	SerDes Transmit Channel Configuration Register 0
02D0 0114	SERDES_CFGTX1_CNTL	SerDes Transmit Channel Configuration Register 1
02D0 0118	SERDES_CFGTX2_CNTL	SerDes Transmit Channel Configuration Register 2
02D0 011C	SERDES_CFGTX3_CNTL	SerDes Transmit Channel Configuration Register 3
02D0 0120	SERDES_CFG0_CNTL	SerDes Macro Configuration Register 0
02D0 0124	SERDES_CFG1_CNTL	SerDes Macro Configuration Register 1
02D0 0128	SERDES_CFG2_CNTL	SerDes Macro Configuration Register 2
02D0 012C	SERDES_CFG3_CNTL	SerDes Macro Configuration Register 3
02D0 0130 - 02D0 01FC	-	Reserved
02D0 0200	DOORBELL0_ICSR	DOORBELL Interrupt Condition Status Register 0
02D0 0204	-	Reserved
02D0 0208	DOORBELL0_ICCR	DOORBELL Interrupt Condition Clear Register 0
02D0 020C	-	Reserved
02D0 0210	DOORBELL1_ICSR	DOORBELL Interrupt Condition Status Register 1
02D0 0214	-	Reserved
02D0 0218	DOORBELL1_ICCR	DOORBELL Interrupt Condition Clear Register 1
02D0 021C	-	Reserved
02D0 0220	DOORBELL2_ICSR	DOORBELL Interrupt Condition Status Register 2
02D0 0224	-	Reserved
02D0 0228	DOORBELL2_ICCR	DOORBELL Interrupt Condition Clear Register 2
02D0 022C	-	Reserved
02D0 0230	DOORBELL3_ICSR	DOORBELL Interrupt Condition Status Register 3
02D0 0234	-	Reserved
02D0 0238	DOORBELL3_ICCR	DOORBELL Interrupt Condition Clear Register 3
02D0 023C	-	Reserved
02D0 0240	RX_CPPI_ICSR	RX CPPI Interrupt Condition Status Register
02D0 0244	-	Reserved
02D0 0248	RX_CPPI_ICCR	RX CPPI Interrupt Condition Clear Register
02D0 024c	-	Reserved
02D0 0250	TX_CPPI_ICSR	TX CPPI Interrupt Condition Status Register
02D0 0254	-	Reserved
02D0 0258	TX_CPPI_ICCR	TX CPPI Interrupt Condition Clear Register
02D0 025C	-	Reserved
02D0 0260	LSU_ICSR	LSU Interrupt Condition Status Register
02D0 0264	-	Reserved
02D0 0268	LSU_ICCR	LSU Interrupt Condition Clear Register
02D0 026C	-	Reserved
02D0 0270	ERR_RST_EVNT_ICSR	Error, Reset, and Special Event Interrupt Condition Status Register
02D0 0274	-	Reserved
02D0 0278	ERR_RST_EVNT_ICCR	Error, Reset, and Special Event Interrupt Condition Clear Register
02D0 027C	-	Reserved
02D0 0280	DOORBELL0_ICRR	DOORBELL0 Interrupt Condition Routing Register
02D0 0284	DOORBELL0_ICRR2	DOORBELL 0 Interrupt Condition Routing Register 2
02D0 0288 - 02D0 028C	-	Reserved
02D0 0290	DOORBELL1_ICRR	DOORBELL1 Interrupt Condition Routing Register
02D0 0294	DOORBELL1_ICRR2	DOORBELL 1 Interrupt Condition Routing Register 2
02D0 0298 - 02D0 029C	-	Reserved
02D0 02A0	DOORBELL2_ICRR	DOORBELL2 Interrupt Condition Routing Register
02D0 02A4	DOORBELL2_ICRR2	DOORBELL 2 Interrupt Condition Routing Register 2
02D0 02A8 - 02D0 02AC	-	Reserved
02D0 02B0	DOORBELL3_ICRR	DOORBELL3 Interrupt Condition Routing Register
02D0 02B4	DOORBELL3_ICRR2	DOORBELL 3 Interrupt Condition Routing Register 2
02D0 02B8 - 02D0 02BC	-	Reserved
02D0 02C0	RX_CPPI_ICRR	Receive CPPI Interrupt Condition Routing Register
02D0 02C4	RX_CPPI_ICRR2	Receive CPPI Interrupt Condition Routing Register 2
02D0 02C8 - 02D0 02CC	-	Reserved
02D0 02D0	TX_CPPI_ICRR	Transmit CPPI Interrupt Condition Routing Register
02D0 02D4	TX_CPPI_ICRR2	Transmit CPPI Interrupt Condition Routing Register 2
02D0 02D8 - 02D0 02DC	-	Reserved
02D0 02E0	LSU_ICRR0	LSU Interrupt Condition Routing Register 0
02D0 02E4	LSU_ICRR1	LSU Interrupt Condition Routing Register 1
02D0 02E8	LSU_ICRR2	LSU Interrupt Condition Routing Register 2
02D0 02EC	LSU_ICRR3	LSU Interrupt Condition Routing Register 3
02D0 02F0	ERR_RST_EVNT_ICRR	Error, Reset, and Special Event Interrupt Condition Routing Register
02D0 02F4	ERR_RST_EVNT_ICRR2	Error, Reset, and Special Event Interrupt Condition Routing Register 2
02D0 02F8	ERR_RST_EVNT_ICRR3	Error, Reset, and Special Event Interrupt Condition Routing Register 3
02D0 02FC	-	Reserved
02D0 0300	INTDST0_DECODE	INTDST Interrupt Status Decode Register 0
02D0 0304	INTDST1_DECODE	INTDST Interrupt Status Decode Register 1
02D0 0308	INTDST2_DECODE	INTDST Interrupt Status Decode Register 2
02D0 030C	INTDST3_DECODE	INTDST Interrupt Status Decode Register 3
02D0 0310	INTDST4_DECODE	INTDST Interrupt Status Decode Register 4
02D0 0314	INTDST5_DECODE	INTDST Interrupt Status Decode Register 5
02D0 0318	INTDST6_DECODE	INTDST Interrupt Status Decode Register 6
02D0 031C	INTDST7_DECODE	INTDST Interrupt Status Decode Register 7
02D0 0320	INTDST0_RATE_CNTL	INTDST Interrupt Rate Control Register 0
02D0 0324	INTDST1_RATE_CNTL	INTDST Interrupt Rate Control Register 1
02D0 0328	INTDST2_RATE_CNTL	INTDST Interrupt Rate Control Register 2
02D0 032C	INTDST3_RATE_CNTL	INTDST Interrupt Rate Control Register 3
02D0 0330	INTDST4_RATE_CNTL	INTDST Interrupt Rate Control Register 4
02D0 0334	INTDST5_RATE_CNTL	INTDST Interrupt Rate Control Register 5
02D0 0338	INTDST6_RATE_CNTL	INTDST Interrupt Rate Control Register 6
02D0 033C	INTDST7_RATE_CNTL	INTDST Interrupt Rate Control Register 7
02D0 0340 - 02D0 03FC	-	Reserved
02D0 0400	LSU1_REG0	LSU1 Control Register 0
02D0 0404	LSU1_REG1	LSU1 Control Register 1
02D0 0408	LSU1_REG2	LSU1 Control Register 2
02D0 040C	LSU1_REG3	LSU1 Control Register 3
02D0 0410	LSU1_REG4	LSU1 Control Register 4
02D0 0414	LSU1_REG5	LSU1 Control Register 5
02D0 0418	LSU1_REG6	LSU1 Control Register 6
02D0 041C	LSU1_FLOW_MASKS1	LSU1 Congestion Control Flow Mask Register
02D0 0420	LSU2_REG0	LSU2 Control Register 0
02D0 0424	LSU2_REG1	LSU2 Control Register 1
02D0 0428	LSU2_REG2	LSU2 Control Register 2
02D0 042C	LSU2_REG3	LSU2 Control Register 3
02D0 0430	LSU2_REG4	LSU2 Control Register 4
02D0 0434	LSU2_REG5	LSU2 Control Register 5
02D0 0438	LSU2_REG6	LSU2 Control Register 6
02D0 043C	LSU2_FLOW_MASKS2	LSU2 Congestion Control Flow Mask Register
02D0 0440	LSU3_REG0	LSU3 Control Register 0
02D0 0444	LSU3_REG1	LSU3 Control Register 1
02D0 0448	LSU3_REG2	LSU3 Control Register 2
02D0 044C	LSU3_REG3	LSU3 Control Register 3
02D0 0450	LSU3_REG4	LSU3 Control Register 4
02D0 0454	LSU3_REG5	LSU3 Control Register 5
02D0 0458	LSU3_REG6	LSU3 Control Register 6
02D0 045C	LSU3_FLOW_MASKS3	LSU3 Congestion Control Flow Mask Register
02D0 0460	LSU4_REG0	LSU4 Control Register 0
02D0 0464	LSU4_REG1	LSU4 Control Register 1
02D0 0468	LSU4_REG2	LSU4 Control Register 2
02D0 046C	LSU4_REG3	LSU4 Control Register 3
02D0 0470	LSU4_REG4	LSU4 Control Register 4
02D0 0474	LSU4_REG5	LSU4 Control Register 5
02D0 0478	LSU4_REG6	LSU4 Control Register 6
02D0 047C	LSU4_FLOW_MASKS4	LSU4 Congestion Control Flow Mask Register
02D0 0480 - 02D0 04FC	-	Reserved
02D0 0500	QUEUE0_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 0
02D0 0504	QUEUE1_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 1
02D0 0508	QUEUE2_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 2
02D0 050C	QUEUE3_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 3
02D0 0510	QUEUE4_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 4
02D0 0514	QUEUE5_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 5
02D0 0518	QUEUE6_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 6
02D0 051C	QUEUE7_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 7
02D0 0520	QUEUE8_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 8
02D0 0524	QUEUE9_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 9
02D0 0528	QUEUE10_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 10
02D0 052C	QUEUE11_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 11
02D0 0530	QUEUE12_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 12
02D0 0534	QUEUE13_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 13
02D0 0538	QUEUE14_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 14
02D0 053C	QUEUE15_TXDMA_HDP	Queue Transmit DMA Head Descriptor Pointer Register 15
02D0 0540 - 02D0 057C	-	Reserved
02D0 0580	QUEUE0_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 0
02D0 0584	QUEUE1_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 1
02D0 0588	QUEUE2_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 2
02D0 058C	QUEUE3_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 3
02D0 0590	QUEUE4_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 4
02D0 0594	QUEUE5_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 5
02D0 0598	QUEUE6_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 6
02D0 059C	QUEUE7_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 7
02D0 05A0	QUEUE8_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 8
02D0 05A4	QUEUE9_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 9
02D0 05A8	QUEUE10_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 10
02D0 05AC	QUEUE11_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 11
02D0 05B0	QUEUE12_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 12
02D0 05B4	QUEUE13_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 13
02D0 05B8	QUEUE14_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 14
02D0 05BC	QUEUE15_TXDMA_CP	Queue Transmit DMA Completion Pointer Register 15
02D0 05D0 - 02D0 05FC	-	Reserved
02D0 0600	QUEUE0_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 0
02D0 0604	QUEUE1_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 1
02D0 0608	QUEUE2_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 2
02D0 060C	QUEUE3_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 3
02D0 0610	QUEUE4_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 4
02D0 0614	QUEUE5_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 5
02D0 0618	QUEUE6_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 6
02D0 061C	QUEUE7_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 7
02D0 0620	QUEUE8_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 8
02D0 0624	QUEUE9_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 9
02D0 0628	QUEUE10_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 10
02D0 062C	QUEUE11_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 11
02D0 0630	QUEUE12_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 12
02D0 0634	QUEUE13_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 13
02D0 0638	QUEUE14_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 14
02D0 063C	QUEUE15_RXDMA_HDP	Queue Receive DMA Head Descriptor Pointer Register 15
02D0 0640 - 02D0 067C	-	Reserved
02D0 0680	QUEUE0_RXDMA_CP	Queue Receive DMA Completion Pointer Register 0
02D0 0684	QUEUE1_RXDMA_CP	Queue Receive DMA Completion Pointer Register 1
02D0 0688	QUEUE2_RXDMA_CP	Queue Receive DMA Completion Pointer Register 2
02D0 068C	QUEUE3_RXDMA_CP	Queue Receive DMA Completion Pointer Register 3
02D0 0690	QUEUE4_RXDMA_CP	Queue Receive DMA Completion Pointer Register 4
02D0 0694	QUEUE5_RXDMA_CP	Queue Receive DMA Completion Pointer Register 5
02D0 0698	QUEUE6_RXDMA_CP	Queue Receive DMA Completion Pointer Register 6
02D0 069C	QUEUE7_RXDMA_CP	Queue Receive DMA Completion Pointer Register 7
02D0 06A0	QUEUE8_RXDMA_CP	Queue Receive DMA Completion Pointer Register 8
02D0 06A4	QUEUE9_RXDMA_CP	Queue Receive DMA Completion Pointer Register 9
02D0 06A8	QUEUE10_RXDMA_CP	Queue Receive DMA Completion Pointer Register 10
02D0 06AC	QUEUE11_RXDMA_CP	Queue Receive DMA Completion Pointer Register 11
02D0 06B0	QUEUE12_RXDMA_CP	Queue Receive DMA Completion Pointer Register 12
02D0 06B4	QUEUE13_RXDMA_CP	Queue Receive DMA Completion Pointer Register 13
02D0 06B8	QUEUE14_RXDMA_CP	Queue Receive DMA Completion Pointer Register 14
02D0 06BC	QUEUE15_RXDMA_CP	Queue Receive DMA Completion Pointer Register 15
02D0 06C0 - 02D0 006FC	-	Reserved
02D0 0700	TX_QUEUE_TEAR_DOWN	Transmit Queue Teardown Register
02D0 0704	TX_CPPI_FLOW_MASKS0	Transmit CPPI Supported Flow Mask Register 0
02D0 0708	TX_CPPI_FLOW_MASKS1	Transmit CPPI Supported Flow Mask Register 1
02D0 070C	TX_CPPI_FLOW_MASKS2	Transmit CPPI Supported Flow Mask Register 2
02D0 0710	TX_CPPI_FLOW_MASKS3	Transmit CPPI Supported Flow Mask Register 3
02D0 0714	TX_CPPI_FLOW_MASKS4	Transmit CPPI Supported Flow Mask Register 4
02D0 0718	TX_CPPI_FLOW_MASKS5	Transmit CPPI Supported Flow Mask Register 5
02D0 071C	TX_CPPI_FLOW_MASKS6	Transmit CPPI Supported Flow Mask Register 6
02D0 0720	TX_CPPI_FLOW_MASKS7	Transmit CPPI Supported Flow Mask Register 7
02D0 0724 - 02D0 073C	-	Reserved
02D0 0740	RX_QUEUE_TEAR_DOWN	Receive Queue Teardown Register
02D0 0744	RX_CPPI_CNTL	Receive CPPI Control Register
02D0 0748 - 02D0 07DC	-	Reserved
02D0 07E0	TX_QUEUE_CNTL0	Transmit CPPI Weighted Round Robin Control Register 0
02D0 07E4	TX_QUEUE_CNTL1	Transmit CPPI Weighted Round Robin Control Register 1
02D0 07E8	TX_QUEUE_CNTL2	Transmit CPPI Weighted Round Robin Control Register 2
02D0 07EC	TX_QUEUE_CNTL3	Transmit CPPI Weighted Round Robin Control Register 3
02D0 07F0 - 02D0 07FC	-	Reserved
02D0 0800	RXU_MAP_L0	Mailbox-to-Queue Mapping Register L0
02D0 0804	RXU_MAP_H0	Mailbox-to-Queue Mapping Register H0
02D0 0808	RXU_MAP_L1	Mailbox-to-Queue Mapping Register L1
02D0 080C	RXU_MAP_H1	Mailbox-to-Queue Mapping Register H1
02D0 0810	RXU_MAP_L2	Mailbox-to-Queue Mapping Register L2
02D0 0814	RXU_MAP_H2	Mailbox-to-Queue Mapping Register H2
02D0 0818	RXU_MAP_L3	Mailbox-to-Queue Mapping Register L3
02D0 081C	RXU_MAP_H3	Mailbox-to-Queue Mapping Register H3
02D0 0820	RXU_MAP_L4	Mailbox-to-Queue Mapping Register L4
02D0 0824	RXU_MAP_H4	Mailbox-to-Queue Mapping Register H4
02D0 0828	RXU_MAP_L5	Mailbox-to-Queue Mapping Register L5
02D0 082C	RXU_MAP_H5	Mailbox-to-Queue Mapping Register H5
02D0 0830	RXU_MAP_L6	Mailbox-to-Queue Mapping Register L6
02D0 0834	RXU_MAP_H6	Mailbox-to-Queue Mapping Register H6
02D0 0838	RXU_MAP_L7	Mailbox-to-Queue Mapping Register L7
02D0 083C	RXU_MAP_H7	Mailbox-to-Queue Mapping Register H7
02D0 0840	RXU_MAP_L8	Mailbox-to-Queue Mapping Register L8
02D0 0844	RXU_MAP_H8	Mailbox-to-Queue Mapping Register H8
02D0 0848	RXU_MAP_L9	Mailbox-to-Queue Mapping Register L9
02D0 084C	RXU_MAP_H9	Mailbox-to-Queue Mapping Register H9
02D0 0850	RXU_MAP_L10	Mailbox-to-Queue Mapping Register L10
02D0 0854	RXU_MAP_H10	Mailbox-to-Queue Mapping Register H10
02D0 0858	RXU_MAP_L11	Mailbox-to-Queue Mapping Register L11
02D0 085C	RXU_MAP_H11	Mailbox-to-Queue Mapping Register H11
02D0 0860	RXU_MAP_L12	Mailbox-to-Queue Mapping Register L12
02D0 0864	RXU_MAP_H12	Mailbox-to-Queue Mapping Register H12
02D0 0868	RXU_MAP_L13	Mailbox-to-Queue Mapping Register L13
02D0 086C	RXU_MAP_H13	Mailbox-to-Queue Mapping Register H13
02D0 0870	RXU_MAP_L14	Mailbox-to-Queue Mapping Register L14
02D0 0874	RXU_MAP_H14	Mailbox-to-Queue Mapping Register H14
02D0 0878	RXU_MAP_L15	Mailbox-to-Queue Mapping Register L15
02D0 087C	RXU_MAP_H15	Mailbox-to-Queue Mapping Register H15
02D0 0880	RXU_MAP_L16	Mailbox-to-Queue Mapping Register L16
02D0 0884	RXU_MAP_H16	Mailbox-to-Queue Mapping Register H16
02D0 0888	RXU_MAP_L17	Mailbox-to-Queue Mapping Register L17
02D0 088C	RXU_MAP_H17	Mailbox-to-Queue Mapping Register H17
02D0 0890	RXU_MAP_L18	Mailbox-to-Queue Mapping Register L18
02D0 0894	RXU_MAP_H18	Mailbox-to-Queue Mapping Register H18
02D0 0898	RXU_MAP_L19	Mailbox-to-Queue Mapping Register L19
02D0 089C	RXU_MAP_H19	Mailbox-to-Queue Mapping Register H19
02D0 08A0	RXU_MAP_L20	Mailbox-to-Queue Mapping Register L20
02D0 08A4	RXU_MAP_H20	Mailbox-to-Queue Mapping Register H20
02D0 08A8	RXU_MAP_L21	Mailbox-to-Queue Mapping Register L21
02D0 08AC	RXU_MAP_H21	Mailbox-to-Queue Mapping Register H21
02D0 08B0	RXU_MAP_L22	Mailbox-to-Queue Mapping Register L22
02D0 08B4	RXU_MAP_H22	Mailbox-to-Queue Mapping Register H22
02D0 08B8	RXU_MAP_L23	Mailbox-to-Queue Mapping Register L23
02D0 08BC	RXU_MAP_H23	Mailbox-to-Queue Mapping Register H23
02D0 08C0	RXU_MAP_L24	Mailbox-to-Queue Mapping Register L24
02D0 08C4	RXU_MAP_H24	Mailbox-to-Queue Mapping Register H24
02D0 08C8	RXU_MAP_L25	Mailbox-to-Queue Mapping Register L25
02D0 08CC	RXU_MAP_H25	Mailbox-to-Queue Mapping Register H25
02D0 08D0	RXU_MAP_L26	Mailbox-to-Queue Mapping Register L26
02D0 08D4	RXU_MAP_H26	Mailbox-to-Queue Mapping Register H26
02D0 08D8	RXU_MAP_L27	Mailbox-to-Queue Mapping Register L27
02D0 08DC	RXU_MAP_H27	Mailbox-to-Queue Mapping Register H27
02D0 08E0	RXU_MAP_L28	Mailbox-to-Queue Mapping Register L28
02D0 08E4	RXU_MAP_H28	Mailbox-to-Queue Mapping Register H28
02D0 08E8	RXU_MAP_L29	Mailbox-to-Queue Mapping Register L29
02D0 08EC	RXU_MAP_H29	Mailbox-to-Queue Mapping Register H29
02D0 08F0	RXU_MAP_L30	Mailbox-to-Queue Mapping Register L30
02D0 08F4	RXU_MAP_H30	Mailbox-to-Queue Mapping Register H30
02D0 08F8	RXU_MAP_L31	Mailbox-to-Queue Mapping Register L31
02D0 08FC	RXU_MAP_H31	Mailbox-to-Queue Mapping Register H31
02D0 0900	FLOW_CNTL0	Flow Control Table Entry Register 0
02D0 0904	FLOW_CNTL1	Flow Control Table Entry Register 1
02D0 0908	FLOW_CNTL2	Flow Control Table Entry Register 2
02D0 090C	FLOW_CNTL3	Flow Control Table Entry Register 3
02D0 0910	FLOW_CNTL4	Flow Control Table Entry Register 4
02D0 0914	FLOW_CNTL5	Flow Control Table Entry Register 5
02D0 0918	FLOW_CNTL6	Flow Control Table Entry Register 6
02D0 091C	FLOW_CNTL7	Flow Control Table Entry Register 7
02D0 0920	FLOW_CNTL8	Flow Control Table Entry Register 8
02D0 0924	FLOW_CNTL9	Flow Control Table Entry Register 9
02D0 0928	FLOW_CNTL10	Flow Control Table Entry Register 10
02D0 092C	FLOW_CNTL11	Flow Control Table Entry Register 11
02D0 0930	FLOW_CNTL12	Flow Control Table Entry Register 12
02D0 0934	FLOW_CNTL13	Flow Control Table Entry Register 13
02D0 0938	FLOW_CNTL14	Flow Control Table Entry Register 14
02D0 093C	FLOW_CNTL15	Flow Control Table Entry Register 15
02D0 0940 - 02D0 09FC	-	Reserved
RapidIO Peripheral-Specific Registers
02D0 1000	DEV_ID	Device Identity CAR
02D0 1004	DEV_INFO	Device Information CAR
02D0 1008	ASBLY_ID	Assembly Identity CAR
02D0 100C	ASBLY_INFO	Assembly Information CAR
02D0 1010	PE_FEAT	Processing Element Features CAR
02D0 1014	-	Reserved
02D0 1018	SRC_OP	Source Operations CAR
02D0 101C	DEST_OP	Destination Operations CAR
02D0 1020 - 02D0 1048	-	Reserved
02D0 104C	PE_LL_CTL	Processing Element Logical Layer Control CSR
02D0 1050 - 02D0 1054	-	Reserved
02D0 1058	LCL_CFG_HBAR	Local Configuration Space Base Address 0 CSR
02D0 105C	LCL_CFG_BAR	Local Configuration Space Base Address 1 CSR
02D0 1060	BASE_ID	Base Device ID CSR
02D0 1064	-	Reserved
02D0 1068	HOST_BASE_ID_LOCK	Host Base Device ID Lock CSR
02D0 106C	COMP_TAG	Component Tag CSR
02D0 1070 - 02D0 10FC	-	Reserved
RapidIO Extended Features -LP Serial Registers
02D0 1100	SP_MB_HEAD	1×/4× LP Serial Port Maintenance Block Header
02D0 1104 - 02D0 1118	-	Reserved
02D0 1120	SP_LT_CTL	Port Link Time-Out Control CSR
02D0 1124	SP_RT_CTL	Port Response Time-Out Control CSR
02D0 1128 - 02D0 1138	-	Reserved
02D0 113C	SP_GEN_CTL	Port General Control CSR
02D0 1140	SP0_LM_REQ	Port 0 Link Maintenance Request CSR
02D0 1144	SP0_LM_RESP	Port 0 Link Maintenance Response CSR
02D0 1148	SP0_ACKID_STAT	Port 0 Local Acknowledge ID Status CSR
02D0 114C - 02D0 1154	-	Reserved
02D0 1158	SP0_ERR_STAT	Port 0 Error and Status CSR
02D0 115C	SP0_CTL	Port 0 Control CSR
02D0 1160	SP1_LM_REQ	Port 1 Link Maintenance Request CSR
02D0 1164	SP1_LM_RESP	Port 1 Link Maintenance Response CSR
02D0 1168	SP1_ACKID_STAT	Port 1 Local Acknowledge ID Status CSR
02D0 116C - 02D0 1174	-	Reserved
02D0 1178	SP1_ERR_STAT	Port 1 Error and Status CSR
02D0 117C	SP1_CTL	Port 1 Control CSR
02D0 1180	SP2_LM_REQ	Port 2 Link Maintenance Request CSR
02D0 1184	SP2_LM_RESP	Port 2 Link Maintenance Response CSR
02D0 1188	SP2_ACKID_STAT	Port 2 Local Acknowledge ID Status CSR
02D0 118C - 02D0 1194	-	Reserved
02D0 1198	SP2_ERR_STAT	Port 2 Error and Status CSR
02D0 119C	SP2_CTL	Port 2 Control CSR
02D0 11A0	SP3_LM_REQ	Port 3 Link Maintenance Request CSR
02D0 11A4	SP3_LM_RESP	Port 3 Link Maintenance Response CSR
02D0 11A8	SP3_ACKID_STAT	Port 3 Local Acknowledge ID Status CSR
02D0 11AC - 02D0 11B4	-	Reserved
02D0 11B8	SP3_ERR_STAT	Port 3 Error and Status CSR
02D0 11BC	SP3_CTL	Port 3 Control CSR
02D0 11C0 -02D0 1FFC	-	Reserved
RapidIO Extended Feature -Error Management Registers
02D0 2000	ERR_RPT_BH	Error Reporting Block Header
02D0 2004	-	Reserved
02D0 2008	ERR_DET	Logical/Transport Layer Error Detect CSR
02D0 200C	ERR_EN	Logical/Transport Layer Error Enable CSR
02D0 2010	H_ADDR_CAPT	Logical/Transport Layer High Address Capture CSR
02D0 2014	ADDR_CAPT	Logical/Transport Layer Address Capture CSR
02D0 2018	ID_CAPT	Logical/Transport Layer Device ID Capture CSR
02D0 201C	CTRL_CAPT	Logical/Transport Layer Control Capture CSR
02D0 2020 - 02D0 2024	-	Reserved
02D0 2028	PW_TGT_ID	Port-Write Target Device ID CSR
02D0 202C - 02D0 203C	-	Reserved
02D0 2040	SP0_ERR_DET	Port 0 Error Detect CSR
02D0 2044	SP0_RATE_EN	Port 0 Error Enable CSR
02D0 2048	SP0_ERR_ATTR_CAPT_DBG0	Port 0 Attributes Error Capture CSR 0
02D0 204C	SP0_ERR_CAPT_DBG1	Port 0 Packet/Control Symbol Error Capture CSR 1
02D0 2050	SP0_ERR_CAPT_DBG2	Port 0 Packet/Control Symbol Error Capture CSR 2
02D0 2054	SP0_ERR_CAPT_DBG3	Port 0 Packet/Control Symbol Error Capture CSR 3
02D0 2058	SP0_ERR_CAPT_DBG4	Port 0 Packet/Control Symbol Error Capture CSR 4
02D0 205C - 02D0 2064	-	Reserved
02D0 2068	SP0_ERR_RATE	Port 0 Error Rate CSR 0
02D0 206C	SP0_ERR_THRESH	Port 0 Error Rate Threshold CSR
02D0 2070 - 02D0 207C	-	Reserved
02D0 2080	SP1_ERR_DET	Port 1 Error Detect CSR
02D0 2084	SP1_RATE_EN	Port 1 Error Enable CSR
02D0 2088	SP1_ERR_ATTR_CAPT_DBG0	Port 1 Attributes Error Capture CSR 0
02D0 208C	SP1_ERR_CAPT_DBG1	Port 1 Packet/Control Symbol Error Capture CSR 1
02D0 2090	SP1_ERR_CAPT_DBG2	Port 1 Packet/Control Symbol Error Capture CSR 2
02D0 2094	SP1_ERR_CAPT_DBG3	Port 1 Packet/Control Symbol Error Capture CSR 3
02D0 2098	SP1_ERR_CAPT_DBG4	Port 1 Packet/Control Symbol Error Capture CSR 4
02D0 209C - 02D0 20A4	-	Reserved
02D0 20A8	SP1_ERR_RATE	Port 1 Error Rate CSR
02D0 20AC	SP1_ERR_THRESH	Port 1 Error Rate Threshold CSR
02D0 20B0 - 02D0 20BC	-	Reserved
02D0 20C0	SP2_ERR_DET	Port 2 Error Detect CSR
02D0 20C4	SP2_RATE_EN	Port 2 Error Enable CSR
02D0 20C8	SP2_ERR_ATTR_CAPT_DBG0	Port 2 Attributes Error Capture CSR 0
02D0 20CC	SP2_ERR_CAPT_DBG1	Port 2 Packet/Control Symbol Error Capture CSR 1
02D0 20D0	SP2_ERR_CAPT_DBG2	Port 2 Packet/Control Symbol Error Capture CSR 2
02D0 20D4	SP2_ERR_CAPT_DBG3	Port 2 Packet/Control Symbol Error Capture CSR 3
02D0 20D8	SP2_ERR_CAPT_DBG4	Port 2 Packet/Control Symbol Error Capture CSR 4
02D0 20DC - 02D0 20E4	-	Reserved
02D0 20E8	SP2_ERR_RATE	Port 2 Error Rate CSR
02D0 20EC	SP2_ERR_THRESH	Port 2 Error Rate Threshold CSR
02D0 20F0 - 02D0 20FC	-	Reserved
02D0 2100	SP3_ERR_DET	Port 3 Error Detect CSR
02D0 2104	SP3_RATE_EN	Port 3 Error Enable CSR
02D0 2108	SP3_ERR_ATTR_CAPT_DBG0	Port 3 Attributes Error Capture CSR 0
02D0 210C	SP3_ERR_CAPT_DBG1	Port 3 Packet/Control Symbol Error Capture CSR 1
02D0 2110	SP3_ERR_CAPT_DBG2	Port 3 Packet/Control Symbol Error Capture CSR 2
02D0 2114	SP3_ERR_CAPT_DBG3	Port 3 Packet/Control Symbol Error Capture CSR 3
02D0 2118	SP3_ERR_CAPT_DBG4	Port 3 Packet/Control Symbol Error Capture CSR 4
02D0 211C - 02D0 2124	-	Reserved
02D0 2128	SP3_ERR_RATE	Port 3 Error Rate CSR
02D0 212C	SP3_ERR_THRESH	Port 3 Error Rate Threshold CSR
02D0 2130 -02D1 0FFC	-	Reserved
Implementation Registers
02D1 1000 - 02D1 1FFC	-	Reserved
02D1 2000	SP_IP_DISCOVERY_TIMER	Port IP Discovery Timer in 4x mode
02D1 2004	SP_IP_MODE	Port IP Mode CSR
02D1 2008	IP_PRESCAL	Port IP Prescaler Register
02D1 200C	-	Reserved
02D1 2010	SP_IP_PW_IN_CAPT0	Port-Write-In Capture CSR Register 0
02D1 2014	SP_IP_PW_IN_CAPT1	Port-Write-In Capture CSR Register 1
02D1 2018	SP_IP_PW_IN_CAPT2	Port-Write-In Capture CSR Register 2
02D1 201C	SP_IP_PW_IN_CAPT3	Port-Write-In Capture CSR Register 3
02D1 2020 - 02D1 3FFC	-	Reserved
02D1 4000	SP0_RST_OPT	Port 0 Reset Option CSR
02D1 4004	SP0_CTL_INDEP	Port 0 Control Independent Register
02D1 4008	SP0_SILENCE_TIMER	Port 0 Silence Timer Register
02D1 400C	SP0_MULT_EVNT_CS	Port 0 Multicast-Event Control Symbol Request Register
02D1 4010	-	Reserved
02D1 4014	SP0_CS_TX	Port 0 Control Symbol Transmit Register
02D1 4018 - 02D1 40FC	-	Reserved
02D1 4100	SP1_RST_OPT	Port 1 Reset Option CSR
02D1 4104	SP1_CTL_INDEP	Port 1 Control Independent Register
02D1 4108	SP1_SILENCE_TIMER	Port 1 Silence Timer Register
02D1 410C	SP1_MULT_EVNT_CS	Port 1 Multicast-Event Control Symbol Request Register
02D1 4110	-	Reserved
02D1 4114	SP1_CS_TX	Port 1 Control Symbol Transmit Register
02D1 4118 - 02D1 41FC	-	Reserved
02D1 4200	SP2_RST_OPT	Port 2 Reset Option CSR
02D1 4204	SP2_CTL_INDEP	Port 2 Control Independent Register
02D1 4208	SP2_SILENCE_TIMER	Port 2 Silence Timer Register
02D1 420C	SP2_MULT_EVNT_CS	Port 2 Multicast-Event Control Symbol Request Register
02D1 4214	SP2_CS_TX	Port 2 Control Symbol Transmit Register
02D1 4218 - 02D1 42FC	-	Reserved
02D1 4300	SP3_RST_OPT	Port 3 Reset Option CSR
02D1 4304	SP3_CTL_INDEP	Port 3 Control Independent Register
02D1 4308	SP3_SILENCE_TIMER	Port 3 Silence Timer Register
02D1 430C	SP3_MULT_EVNT_CS	Port 3 Multicast-Event Control Symbol Request Register
02D1 4310	-	Reserved
02D1 4314	SP3_CS_TX	Port 3 Control Symbol Transmit Register
02D1 4318 - 02D2 0FFF	-	Reserved
02D2 1000 - 02DF FFFF	-	Reserved

4.7.17.3 Serial RapidIO Electrical Data/Timing

The TMS320TCI6484 and TMS320C6457 SerDes Implementation Guidelines application report (SPRAAY1) specifies a complete printed circuit board (PCB) solution for the C6457 as well as a list of compatible SRIO devices showing two DSPs connected via a 4× SRIO link. TI has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

Serial RapidIO is electrically compliant with the RapidIO™ Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.

4.7.18 General-Purpose Input/Output (GPIO)

4.7.18.1 GPIO Device-Specific Information

On the C6457, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more detailed information on device/peripheral configuration and the C6457 device pin muxing, see Section 5.5.

4.7.18.2 GPIO Peripheral Register Description(s)

Table 4-97 GPIO Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
02B0 0008	BINTEN	GPIO interrupt per bank enable register
02B0 000C	-	Reserved
02B0 0010	DIR	GPIO Direction Register
02B0 0014	OUT_DATA	GPIO Output Data register
02B0 0018	SET_DATA	GPIO Set Data register
02B0 001C	CLR_DATA	GPIO Clear Data Register
02B0 0020	IN_DATA	GPIO Input Data Register
02B0 0024	SET_RIS_TRIG	GPIO Set Rising Edge Interrupt Register
02B0 0028	CLR_RIS_TRIG	GPIO Clear Rising Edge Interrupt Register
02B0 002C	SET_FAL_TRIG	GPIO Set Falling Edge Interrupt Register
02B0 0030	CLR_FAL_TRIG	GPIO Clear Falling Edge Interrupt Register
02B0 008C	-	Reserved
02B0 0090 - 02B0 00FF	-	Reserved
02B0 0100 - 02B0 3FFF	-	Reserved

4.7.18.3 GPIO Electrical Data/Timing

Table 4-98 GPIO Input Timing Requirements⁽¹⁾

(see Figure 4-66)

NO.			MIN	MAX	UNIT
1	t_w(GPOH)	Pulse duration, GPOx high	12C		ns
2	t_w(GPOL)	Pulse duration, GPOx low	12C		ns

(1) If CORECLKSEL = 0, C = 1 ÷ CORECLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency, in ns.

Table 4-99 GPIO Output Switching Characteristics⁽¹⁾⁽²⁾

(see Figure 4-66)

NO.	PARAMETER		MIN	MAX	UNIT
1	t_w(GPOH)	Pulse duration, GPOx high	12C - 3		ns
2	t_w(GPOL)	Pulse duration, GPOx low	12C - 3		ns

(1) Over recommended operating conditions.

(2) If CORECLKSEL = 0, C = 1 ÷ CORECLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency, in ns.

Figure 4-66 GPIO Timing

4.7.19 Emulation Features and Capability

4.7.19.1 Advanced Event Triggering (AET)

The C6457 device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities:

Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.
Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture.
Counters: count the occurrence of an event or cycles for performance monitoring.
State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.

For more information on AET, see the following documents:

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report (SPRA753)
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems application report (SPRA387)

4.7.19.2 Trace

The C6457 device supports Trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system.

For more information on board design guidelines for Trace Advanced Emulation, see the 60-Pin Emulation Header Technical Reference (SPRU655).

4.7.19.2.1 Trace Electrical Data/Timing

Table 4-100 Switching Characteristics for Trace ⁽¹⁾

(see Figure 4-67)

NO.	PARAMETER		MIN	MAX	UNIT
1	t_w(DPnH)	Pulse duration, DPn/EMUn high	2.4		ns
1	t_w(DPnH)90%	Pulse duration, DPn/EMUn high detected at 90% Voh	1.5		ns
2	t_w(DPnL)	Pulse duration, DPn/EMUn low	2.4		ns
2	t_w(DPnL)10%	Pulse duration, DPn/EMUn low detected at 10% Voh	1.5		ns
3	t_sko(DPn)	Output skew time, time delay difference between DPn/EMUn pins configured as trace	-500	500	ps

(1) Over recommended operating conditions.

Figure 4-67 Trace Timing

4.7.19.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).

4.7.19.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6457 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

4.7.19.3.2 JTAG Electrical Data/Timing

Table 4-101 JTAG Test Port Timing Requirements

(see Figure 4-68)

NO.			MIN	MAX	UNIT
1	t_c(TCK)	Cycle time, TCK	10	20	ns
3	t_{su(TDIV-TCKH)}	Setup time, TDI/TMS/TRST valid before TCK high	2		ns
4	t_h(TCKH-TDIV)	Hold time, TDI/TMS/TRST valid after TCK high	5		ns

Table 4-102 JTAG Test Port Switching Characteristics⁽¹⁾

(see Figure 4-68)

NO.	PARAMETER		MIN	MAX	UNIT
2	t_d(TCKL-TDOV)	Delay time, TCK low to TDO valid		0.25 x t_c(TCK)	ns

(1) Over recommended operating conditions.

SM320C6457-HIREL JTAG_Test-Port_Timing_6484.gif

Figure 4-68 JTAG Test-Port Timing

4.7.19.3.3 HS-RTDX Electrical Data/Timing

Table 4-103 Timing Requirements for HS-RTDX

(see Figure 4-69)

NO.			MIN	UNIT
1	t_c(TCK)	Cycle time, TCK	20	ns
2	t_{su(TDIV-TCKH)}	Setup time, EMUn valid before TCK high	1.5	ns
3	t_h(TCKH-TDIV)	Hold time, EMUn valid after TCK high	1.5	ns

Table 4-104 Switching Characteristics for HS-RTDX⁽¹⁾

(see Figure 4-69)

NO.	PARAMETER		MIN	MAX	UNIT
4	t_d(TCKL-TDOV)	Delay time, TCK high to EMUn valid	3	16.5	ns

(1) Over recommended operating conditions.

SM320C6457-HIREL HS-RTDX_Timing_6484.gif

Figure 4-69 HS-RTDX Timing

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4 Specifications

4.1 Absolute Maximum Ratings

4.2 ESD Ratings

4.3 Recommended Operating Conditions

4.4 Electrical Characteristics

4.5 Thermal Resistance Characteristics

Table 4-1 Thermal Resistance Characteristics GMH Package

4.6 Timing and Switching Characteristics

4.6.1 Timing Parameters and Information

4.6.1.1 1.8-V Signal Transition Levels

4.6.1.2 3.3-V Signal Transition Levels

4.6.1.3 3.3-V Signal Transition Rates

4.6.1.4 Timing Parameters and Board Routing Analysis

Table 4-2 Board-Level Timing Example

4.6.2 Power Supply Sequencing

Table 4-3 Timing Requirements for Power Supply Sequence

4.6.2.1 Power-Supply Decoupling

4.6.2.2 Power-Down Operation

4.6.2.3 Power Supply to Peripheral I/O Mapping

4.6.3 Reset Timing

Table 4-4 Reset Timing Requirements(1)(2)

Table 4-5 Reset Switching Characteristics Over Recommended Operating Conditions

Table 4-6 Warm Reset Switching Characteristics Over Recommended Operating Conditions

4.6.4 Clock and Control Signal Transition Behavior

4.7 Peripherals

4.7.1 Enhanced Direct Memory Access (EDMA3) Controller

4.7.1.1 EDMA3 Device-Specific Information

4.7.1.2 EDMA3 Channel Synchronization Events

Table 4-7 C6457 EDMA3 Channel Synchronization Events(1)

4.7.1.3 EDMA3 Peripheral Register Description(s)

Table 4-8 EDMA3 Registers

Table 4-9 EDMA3 Parameter RAM

Table 4-10 EDMA3 Transfer Controller 0 Registers

Table 4-11 EDMA3 Transfer Controller 1 Registers

Table 4-12 EDMA3 Transfer Controller 2 Registers

Table 4-13 EDMA3 Transfer Controller 3 Registers

Table 4-14 EDMA3 Transfer Controller 4 Registers

Table 4-15 EDMA3 Transfer Controller 5 Registers

4.7.2 Interrupts

4.7.2.1 Interrupt Sources and Interrupt Controller

Table 4-16 C6457 System Event Mapping

4.7.2.2 External Interrupts Electrical Data/Timing

Table 4-17 Timing Requirements for External Interrupts(1)

4.7.3 Reset Controller

Table 4-18 Reset Types

4.7.3.1 Power-on Reset (POR Pin)

4.7.3.2 Warm Reset (RESET Pin)

4.7.3.3 System Reset

4.7.3.4 CPU Reset

4.7.3.5 Reset Priority

4.7.3.6 Reset Controller Register

4.7.3.6.1 Reset Type Status Register

Table 4-19 Reset Type Status Register (RSTYPE) Field Descriptions

4.7.3.6.2 Software Reset Control Register

Table 4-20 Software Reset Control Register Field Descriptions

4.7.3.6.3 Reset Configuration Register

Table 4-21 Reset Configuration Register (RSTCFG) Field Descriptions

4.7.4 PLL1 and PLL1 Controller

4.7.4.1 PLL1 Controller Device-Specific Information

4.7.4.1.1 Internal Clocks and Maximum Operating Frequencies

Table 4-22 Timing Requirements for Reset

4.7.4.1.2 PLL1 Controller Operating Modes

4.7.4.1.3 PLL1 Stabilization, Lock, and Reset Times

Table 4-23 PLL1 Stabilization, Lock, and Reset Times

4.7.4.2 PLL1 Controller Memory Map

Table 4-24 PLL1 Controller Registers (Including Reset Controller)

4.7.4.3 PLL1 Controller Registers

4.7.4.3.1 PLL1 Control Register

Table 4-25 PLL1 Control Register (PLLCTL) Field Descriptions

4.7.4.3.2 PLL Multiplier Control Register

Table 4-26 PLL Multiplier Control Register (PLLM) Field Descriptions

4.7.4.3.3 PLL Post-Divider Control Register

Table 4-27 PLL Post-Divider Control Register (POSTDIV) Field Descriptions

4.7.4.3.4 PLL Controller Divider 3 Register

Table 4-28 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions

4.7.4.3.5 PLL Controller Divider 6 Register

Table 4-4 Reset Timing Requirements⁽¹⁾⁽²⁾

Table 4-7 C6457 EDMA3 Channel Synchronization Events⁽¹⁾

Table 4-17 Timing Requirements for External Interrupts⁽¹⁾

Table 4-37 CORECLK(N|P) and ALTCORECLK Timing Requirements⁽¹⁾

Table 4-39 Timing Requirements for DDRREFCLK(N|P) and ALTDDRCLK⁽¹⁾

Table 4-42 EMIFA AECLKIN Timing Requirements⁽¹⁾⁽²⁾

Table 4-43 EMIFA AECLKOUT Switching Characteristics⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

Table 4-44 EMIFA Asynchronous Memory Read Switching Characteristics⁽¹⁾⁽²⁾

Table 4-46 EMIFA Asynchronous Memory Write Timing Requirements⁽¹⁾⁽²⁾

Table 4-47 EMIFA EM_Wait Read Timing Requirements⁽¹⁾

Table 4-48 EMIFA EM_Wait Read Switching Characteristics⁽¹⁾

Table 4-51 Switching Characteristics for Programmable Synchronous Interface Cycles for EMIFA Module⁽¹⁾

4.7.8 I²C Peripheral

4.7.8.1 I²C Device-Specific Information

4.7.8.2 I²C Peripheral Register Description(s)

Table 4-52 I²C Registers

4.7.8.3 I²C Electrical Data/Timing

4.7.8.3.1 Inter-Integrated Circuits (I²C) Timing

Table 4-53 I²C Timing Requirements⁽¹⁾

Table 4-54 I²C Switching Characteristics⁽¹⁾

Table 4-57 Host-Port Interface Timing Requirements⁽¹⁾⁽²⁾

Table 4-58 Host-Port Interface Switching Characteristics⁽¹⁾⁽²⁾

Table 4-61 McBSP Timing Requirements⁽¹⁾