SBOS708C May   2016  – April 2026 REF60

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-A787C102-7D46-49D3-80D0-980BFF94C990/SBOS600118
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Solder Heat Shift
    2. 7.2 Thermal Hysteresis
    3. 7.3 Reference Droop Measurements
    4. 7.4 1/f Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Integrated ADC Drive Buffer
      2. 8.3.2 Temperature Drift
      3. 8.3.3 Load Current
      4. 8.3.4 Stability
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Results
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.4.1 Layout Guidelines

Figure 9-9 illustrates an example of a PCB layout for a data-acquisition system using the REF60xx. Some key considerations are:

  • Connect low-ESR, 0.1μF ceramic bypass capacitors between the VIN pin and ground.
  • Place the REF60xx output capacitor (CL) and the ADC as close to each other as possible.
  • Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 9-9.
  • Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output capacitor CL, as shown in Figure 9-9.
  • Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.