SBOS392I August   2007  – April 2026

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Thermal Hysteresis
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-Up Time
      2. 8.3.2 Low Temperature Drift
      3. 8.3.3 Power Dissipation
      4. 8.3.4 Noise Performance
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 REF3312 in a Bipolar Signal-Chain Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Op Amp Level-Shift Design
          2. 9.2.1.2.2 Differential Input Attenuator Design
          3. 9.2.1.2.3 Input Filtering
          4. 9.2.1.2.4 Component Selection
            1. 9.2.1.2.4.1 Voltage References
            2. 9.2.1.2.4.2 Op Amp
          5. 9.2.1.2.5 Input Attenuation and Level Shifting
          6. 9.2.1.2.6 Input Filtering
          7. 9.2.1.2.7 Passive Component Tolerances and Materials
        3. 9.2.1.3 Application Curves
          1. 9.2.1.3.1 DC Performance
          2. 9.2.1.3.2 AC Performance
    3. 9.3 Power-Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.2.1.3.1 DC Performance

The measured dc performance and calculated error of the circuit is shown in Figure 9-2 and Figure 9-3, respectively. By applying a two-point gain and offset calibration over the specified ±5V input range, the calibrated error is shown in Figure 9-4. The uncalibrated results show errors of 138μV, or 0.0138%FSR. The calibrated results with a simple two-point calibration show errors under 5μV, or 0.0005%FSR, in the specified input range of ±5V.

REF33 Measured DC Transfer Function with ±6V Input
Figure 9-2 Measured DC Transfer Function with ±6V Input
REF33 Calibrated Output Error with ±6V Input
Figure 9-4 Calibrated Output Error with ±6V Input
REF33 Measured Output Error with ±6V Input
Figure 9-3 Measured Output Error with ±6V Input