SBOS392I August   2007  – April 2026

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Thermal Hysteresis
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-Up Time
      2. 8.3.2 Low Temperature Drift
      3. 8.3.3 Power Dissipation
      4. 8.3.4 Noise Performance
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 REF3312 in a Bipolar Signal-Chain Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Op Amp Level-Shift Design
          2. 9.2.1.2.2 Differential Input Attenuator Design
          3. 9.2.1.2.3 Input Filtering
          4. 9.2.1.2.4 Component Selection
            1. 9.2.1.2.4.1 Voltage References
            2. 9.2.1.2.4.2 Op Amp
          5. 9.2.1.2.5 Input Attenuation and Level Shifting
          6. 9.2.1.2.6 Input Filtering
          7. 9.2.1.2.7 Passive Component Tolerances and Materials
        3. 9.2.1.3 Application Curves
          1. 9.2.1.3.1 DC Performance
          2. 9.2.1.3.2 AC Performance
    3. 9.3 Power-Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.2.1.2.6 Input Filtering

The MSP430 ADC is configured to run from the 1.1MHz SMCLK with an oversampling rate (OSR) of 256, yielding a sample rate of roughly 4.3kHz. The input filter cutoff frequency is set to 1kHz to limit the input signal bandwidth, as shown in Equation 19. R8 is 1kΩ to provide isolation from the capacitive load of the low-pass filter, thereby reducing stability concerns.

Equation 18. f - 3 d B _ A 1 + = 1 k H z = 1 2 × π × R 8 × C 1

where

Equation 19. C 1 = 1 2 × π × 1 k Ω × 1 k H z = 159 n F

Reduce C1 to 150nF so that it is a standard value.

The A1– input of the delta-sigma (ΔΣ) converter is not buffered, and therefore requires a large capacitor to supply the charge for the internal sampling capacitor. A 47μF capacitor is selected, resulting in the cutoff frequency illustrated in Equation 20.

Equation 20. f - 3 d B _ A 1 - = 1 2 × π × R 6 2 × C 2 = 0.144 H z

In applications that cannot tolerate such a low-frequency cutoff, and therefore a long start-up time, buffer the A1– input with another OPA317 to properly drive the ADC input with a lower-input capacitor.