ZHCSNM0F September   2006  – March 2021 PCA9554A

PRODUCTION DATA  

  1. 1 特性
  2. 2 说明
  3. 3 Revision History
  4. 4 Description (Continued)
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
      1. 8.2.1 Power-On Reset
      2. 8.2.2 I/O Port
      3. 8.2.3 Interrupt Output ( INT)
        1. 8.2.3.1 Interrupt Errata
          1. 8.2.3.1.1 Description
          2. 8.2.3.1.2 System Impact
          3. 8.2.3.1.3 System Workaround
    3. 8.3 Programming
      1. 8.3.1 I2C Interface
      2. 8.3.2 Register Map
        1. 8.3.2.1 Device Address
        2. 8.3.2.2 Control Register And Command Byte
        3. 8.3.2.3 Register Descriptions
        4. 8.3.2.4 Bus Transactions
          1. 8.3.2.4.1 Writes
          2. 8.3.2.4.2 Reads
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Detailed Design Procedure
          1. 9.1.1.1.1 Minimizing ICC When I/Os Control Leds
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Device and Documentation Support
    1. 11.1 支持资源
    2. 11.2 Trademarks
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration And Functions

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Table 5-1 Pin Functions
PIN DESCRIPTION
NAME QSOP (DBQ)
SOIC (DW),
SSOP (DB),
TSSOP (PW), AND
TVSOP (DGV)		 QFN (RGT AND
RGV)
A0 1 15 Address input. Connect directly to VCC or ground.
A1 2 16 Address input. Connect directly to VCC or ground.
A2 3 1 Address input. Connect directly to VCC or ground.
P0 4 2 P-port input/output. Push-pull design structure.
P1 5 3 P-port input/output. Push-pull design structure.
P2 6 4 P-port input/output. Push-pull design structure.
P3 7 5 P-port input/output. Push-pull design structure.
GND 8 6 Ground
P4 9 7 P-port input/output. Push-pull design structure.
P5 10 8 P-port input/output. Push-pull design structure.
P6 11 9 P-port input/output. Push-pull design structure.
P7 12 10 P-port input/output. Push-pull design structure.
INT 13 11 Interrupt output. Connect to VCC through a pullup resistor.
SCL 14 12 Serial clock bus. Connect to VCC through a pullup resistor.
SDA 15 13 Serial data bus. Connect to VCC through a pullup resistor.
VCC 16 14 Supply voltage