ZHCSNM0F September   2006  – March 2021 PCA9554A

PRODUCTION DATA  

  1. 特性
  2. 说明
  3. Revision History
  4. Description (Continued)
  5. Pin Configuration And Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
      1. 8.2.1 Power-On Reset
      2. 8.2.2 I/O Port
      3. 8.2.3 Interrupt Output ( INT)
        1. 8.2.3.1 Interrupt Errata
          1. 8.2.3.1.1 Description
          2. 8.2.3.1.2 System Impact
          3. 8.2.3.1.3 System Workaround
    3. 8.3 Programming
      1. 8.3.1 I2C Interface
      2. 8.3.2 Register Map
        1. 8.3.2.1 Device Address
        2. 8.3.2.2 Control Register And Command Byte
        3. 8.3.2.3 Register Descriptions
        4. 8.3.2.4 Bus Transactions
          1. 8.3.2.4.1 Writes
          2. 8.3.2.4.2 Reads
  9. Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Detailed Design Procedure
          1. 9.1.1.1.1 Minimizing ICC When I/Os Control Leds
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Device and Documentation Support
    1. 11.1 支持资源
    2. 11.2 Trademarks
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Control Register And Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9554A. Two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent.

GUID-DB0448E5-7311-48DB-9F5F-821C432C1508-low.gifFigure 8-7 Control Register Bits
Table 8-3 Command Byte
CONTROL REGISTER BITSCOMMAND BYTE
(HEX)
REGISTERPROTOCOLPOWER-UP
DEFAULT
B1B0
000x00Input PortRead byteXXXX XXXX
010x01Output PortRead/write byte1111 1111
100x02Polarity InversionRead/write byte0000 0000
110x03ConfigurationRead/write byte1111 1111