ZHCSOI9A July   2022  – December 2022 OPA817

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Typical Characteristics: VS = ±5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 FET-Input Architecture with Wide Gain-Bandwidth Product
      4. 8.3.4 Device Functional Modes
        1. 8.3.4.1 Power-Down (PD) Pin
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Wideband, High-Input Impedance DAQ Front-End
    2. 9.2 Typical Applications
      1. 9.2.1 High Input Impedance, 200 MHz, Digitizer Front-End Amplifier Design
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.3.4.1 Power-Down (PD) Pin

The OPA817 includes a power-down mode for low-power or standby operation and only consumes 55 μA (typical) of current when placed in power-down mode. Low-power systems that are only active for small periods of time benefit from this feature. The OPA817 can transition from low-power mode to active-mode in 300 ns (typical). For power-down pin control thresholds, refer to Section 7.5. An internal pull-up resistor of 2-MΩ provides a weak pull-up to VS+ if PD is left unconnected. An external 1-nF capacitor to VS+ may be used to avoid external noise coupling and false triggering. If the power-down mode is not used in an application, then connect the PD pin to VS+.