SBOS293H December   2003  – December 2015 OPA695

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Small Signal Measurement
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wideband Current Feedback Operation
      2. 8.3.2 RF Specifications and Applications
      3. 8.3.3 Input Return Loss (S11)
      4. 8.3.4 Output Return Loss (S22)
      5. 8.3.5 Forward Gain (S21)
      6. 8.3.6 Reverse Isolation (S12)
      7. 8.3.7 Limits to Dynamic Range
        1. 8.3.7.1 -1-dB Compression
        2. 8.3.7.2 Two-Tone 3rd-Order Output Intermodulation Intercept (OP3)
        3. 8.3.7.3 Noise Figure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SAW Filter Buffer
      2. 9.1.2 LO Buffer Amplifier
      3. 9.1.3 Wideband Cable Driving Applications
        1. 9.1.3.1 Cable Modem Return Path Driver
        2. 9.1.3.2 RGB Video Line Driver
        3. 9.1.3.3 Arbitrary Waveform Driver
      4. 9.1.4 Differential I/O Applications
      5. 9.1.5 Operating Suggestions
        1. 9.1.5.1 Setting Resistor Values to Optimize Bandwidth
        2. 9.1.5.2 Output Current and Voltage
        3. 9.1.5.3 Driving Capacitive Loads
        4. 9.1.5.4 Distortion Performance
        5. 9.1.5.5 Noise Performance
        6. 9.1.5.6 DC Accuracy and Offset Control
        7. 9.1.5.7 Power Shutdown Operation
        8. 9.1.5.8 Thermal Analysis
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Saw Filter Buffer
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Input and ESD Protection
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Design-In Tools
        1. 12.1.1.1 Demonstration Fixtures
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Power supply ±6.5 V
Internal power dissipation See Thermal Analysis
Differential input voltage ±1.2 V
Input common-mode voltage ±VS V
TJ Junction temperature 150 °C
Tstg Storage temperature; D, DBV –65 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
OPA695 in DGK or D package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except pin 2 ±1500 V
Pin 2 ±500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000
Machine Model (MM) All pins ±100
OPA695 in DBV package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except pin 4 ±1500 V
Pin 4 ±500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000
Machine Model (MM) All pins ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Split supply voltage ±2.5 ±5 ±6 V
VS Single supply voltage 5 10 12 V
TA Ambient temperature –40 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) OPA695 UNIT
D (SOIC) DGK (VSSOP) DBV (SOT-23)
8 PINS 8 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 125 135 150 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 63 81 108 °C/W
RθJB Junction-to-board thermal resistance 58 56 26.4 °C/W
ψJT Junction-to-top characterization parameter 12 8.5 15 °C/W
ψJB Junction-to-board characterization parameter 57 48 26 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — —
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

RF = 348 Ω, RL = 100 Ω to VS/2, and G = +8, (see Figure 50 for AC performance only), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL
(3)
AC PERFORMANCE (see Gain 2V/V Video Line Driver)
Small-signal bandwidth
(VO = 0.5 VPP) 		G = +1, RF = 523 Ω 25°C 1700 MHz C
G = +2, RF = 511 Ω 25°C 1400 C
G = +8, RF = 402 Ω 25°C(1) 400 450 B
0°C to 70°C(2) 380
–40°C to +85°C(2) 350
G = +16, RF = 249 Ω 25°C 350 C
Bandwidth for 0.2-dB gain flatness G = +2, VO = 0.5 VPP, RF =523 Ω 25°C 320 MHZ B
Peaking at a gain of +1 RF = 523 Ω, VO = 0.5 VPP 25°C(1) 4.6 5.4 dB B
0°C to 70°C(2) 5.8
–40°C to +85°C(2) 6
Large-signal bandwidth G = +8, VO = 4 VPP 25°C 450 MHz c
Slew Rate G = –8, VO = 4-V Step 25°C(1) 3700 4300 V/μs B
0°C to 70°C(2) 3600
–40°C to +85°C(2) 3500
G = +8, VO = 4-V Step 25°C(1) 2600 2900
0°C to 70°C(2) 2500
–40°C to +85°C(2) 2400
Rise-and-fall time G = +8, VO = 0.5-V Step 25°C 0.8 ns C
G = +8, VO = 4-V Step 25°C 1
Settling time to 0.02% G = +8, VO = 2-V Step 25°C 16 ns C
to 0.1% 25°C 10
Harmonic distortion (G = +8, f = 10 MHz, VO = 2 VPP) 2nd-harmonic RL = 100 Ω 25°C(1) –65 –62 dBc B
0°C to 70°C(2) –60
–40°C to +85°C(2) –59
RL ≥ 500 Ω 25°C(1) –78 –76
0°C to 70°C(2) –74
–40°C to +85°C(2) –73
3rd-harmonic RL = 100 Ω 25°C(1) –86 –84
0°C to 70°C(2) –75
–40°C to +85°C(2) –72
RL ≥ 500 Ω 25°C(1) –86 –82
0°C to 70°C(2) –81
–40°C to +85°C(2) –80
Input voltage noise f > 1 MHz 25°C(1) 1.8 2 nV/√Hz B
0°C to 70°C(2) 2.7
–40°C to +85°C(2) 2.9
Noninverting input current noise f > 1 MHz 25°C(1) 18 19 nV/√Hz B
0°C to 70°C(2) 21
–40°C to +85°C(2) 22
Inverting input current noise f > 1 MHz 25°C(1) 22 24 pA/√Hz B
0°C to 70°C(2) 26
–40°C to +85°C(2) 27
Differential gain G = +2, NTSC, VO = 1.4 Vp,
RL = 150 Ω		 25°C 0.04% C
Differntial phase G = +2, NTSC, VO = 1.4 Vp,
RL = 150 Ω		 25°C 0.007 deg deg
DC PERFORMANCE(4)
Open-loop transimpedance gain (ZOL) VO = 0 V, RL = 100 25°C(1) 45(6) 85 kΩ A
0°C to 70°C(2) 43
–40°C to +85°C(2) 41
Input offset voltage VCM = 0 V 25°C(1) ±0.3 ±3.0(6) mV A
0°C to 70°C(2) ±3.5
–40°C to +85°C(2) ±4
Average offset voltage drift VCM = 0 V 0°C to 70°C(2) ±10 μV/°C B
–40°C to +85°C(2) ±15
Noninverting input bias current VCM = 0 V 25°C(1) ±13 ±30(6) μA A
0°C to 70°C(2) ±37
–40°C to +85°C(2) ±41
Average noninventing input bias current drift VCM = 0 V 0°C to 70°C(2) 150 µA A
–40°C to +85°C(2) 150
Inverting input bias current VCM = 0 V 25°C(1) ±20 ±60(6) µA A
0°C to 70°C(2) ±66
–40°C to +85°C(2) ±70
Average inventing bias current drift VCM = 0 V 0°C to 70°C(2) ±120 nA/°C B
–40°C to +85°C(2) ±160
INPUT
Common-mode input range(5) (CMIR) 25°C(1) ±3.1(6) ±3.3 V A
0°C to 70°C(2) ±3
–40°C to +85°C(2) ±3
Common-mode rejection ratio (CMRR) VCM = 0 V 25°C(1) 51(6) 56 dB A
0°C to 70°C(2) 50
–40°C to +85°C(2) 50
Noninverting input impedance 25°C(1) 280 || 1.2 kΩ || pF C
Inverting input resistance (Rl) Open-loop 25°C(1) 29 Ω C
OUTPUT
Voltage output swing No load 25°C(1) ±4(6) ±4.2 V A
0°C to 70°C(2) ±3.9
–40°C to +85°C(2) ±3.9
100-Ω load 25°C(1) ±3.7(6) ±3.9
0°C to 70°C(2) ±3.7
–40°C to +85°C(2) ±3.6
Current output, sourcing VO = 0 25°C(1) 90(6) 120 mA A
0°C to 70°C(2) 80
–40°C to +85°C(2) 70
Current output, sinking VO = 0 25°C(1) 90(6) mA A
0°C to 70°C(2) –80
–40°C to
+85°C(2)		 –70
Closed-loop output impedance G = +8, f = 100 kHz 25°C 0.04 Ω C
DISABLE (Disabled LOW)
Power-down supply current (+VS) VDIS = 0 25°C –100 µA A
25°C(1) –170(6)
0°C to 70°C(2) –186
–40°C to +85°C(2) –192
Disable time VIN = ±0.25 VDC 25°C 1 µs C
Enable time VIN = ±0.25 VDC 25°C 1 ns C
Off isolation G = +8, 10 MHz 25°C 70 dB C
Output capacitance in disable 25°C 4 pF C
Turn on glitch G = +2, RL = 150 Ω, VIN = 0 25°C ±100 mV C
Turn off glitch G = +2, RL = 150 Ω, VIN = 0 25°C ±20 mV C
Enable voltage 25°C(1) 3.5(6) 3.3 V A
0°C to 70°C(2) 3.6
–40°C to +85°C(2) 3.7
Disable voltage 25°C(1) 1.8 1.7(6) V A
0°C to 70°C(2) 1.6
–40°C to +85°C(2) 1.5
Control pin input bias current (DIS) VDIS = 0 25°C(1) 75 130(6) µA A
0°C to 70°C(2) 143
–40°C to +85°C(2) 145
POWER SUPPLY
Specified operating voltage 25°C ±5 V C
Maximum operating voltage range 25°C(1) ±6(6) V A
0°C to 70°C(2) ±6
–40°C to +85°C(2) ±6
Maximum quiescent VS = ±5 V 25°C 12.9 mA A
25°C(1) 13.3(6)
0°C to 70°C(2) 13.7
–40°C to +85°C(2) 14.1
Minimum quiescent current VS = ±5 V 25°C 12.9 mA A
25°C(1) 12.6(6)
0°C to 70°C(2) 11.8
–40°C to +85°C(2) 11
Power-supply rejection radio (–PSRR) Input referred 25°C 55 dB A
25°C(1) 51(6)
0°C to 70°C(2) 48
–40°C to +85°C(2) 48
TEMPERATURE RANGE
Specification: ID, IDBV 25°C –40 to 85 °C C
AC PERFORMANCE (see Figure 50)
Small-signal bandwidth
(VO = 0.5 VPP)		 G = +1, RF = 511 Ω 25°C 1400 MHz C
G = +2, RF = 487 Ω 25°C 960 C
G = +8, RF = 348 Ω 25°C 395 B
25°C(1) 980
0°C to 70°C(2) 330
–40°C to +85°C(2) 300
G = +16, RF = 162 Ω 25°C 235 C
Bandwith for 0.2-dB gain flatness G = +2, VO <0.5 VPP, RF = 487Ω 25°C 230 MHz B
25°C(1) 180
0°C to 70°C(2) 135
–40°C to +85°C(2) 110
Peaking at a gain of +1 VO <0.5 VPP, RF = 511 Ω 25°C 1 dB B
25°C(1) 2
0°C to 70°C(2) 2.5
–40°C to +85°C(2) 3
Large-signal bandwidth G = +8, VO = 2 VPP 25°C 310 MHz C
Slew rate G = +8, 2-V Step 25°C 1700 v/μs B
25°C(1) 1300
0°C to 70°C(2) 1200
–40°C to +85°C(2) 1100
Rise-and-fall-time G = +8, VO = 0.5-V Step 25°C 1 ns C
G = +8, VO = 2-V Step 25°C 1
Settling time to 0.02% G = +8, VO = 2-V Step 25°C 16 ns C
to 0.1% G = +8, VO = 2-V Step 25°C 10
Harmonic distortion
(G = +8, f = 10 MHz, VO = 2 VPP)		 2nd-Harmonic RL = 100 Ω to VS/2 25°C –62 dBc B
25°C(1) –58
0°C to 70°C(2) –58
–40°C to +85°C(2) –57
RL ≥ 500 Ω to VS/2 25°C –70
25°C(1) –66
0°C to 70°C(2) –66
–40°C to +85°C(2) –65
3rd-Harmonic RL = 100 Ω to VS 25°C –66
25°C(1) –64
0°C to 70°C(2) –64
–40°C to +85°C(2) –63
RL ≥ 500 Ω to VS 25°C –65
25°C(1) –63
0°C to 70°C(2) –63
–40°C to +85°C(2) –62
Input voltage noise f > 1 MHz 25°C 1.8 nV/√Hz B
25°C(1) 2
0°C to 70°C(2) 2.7
–40°C to +85°C(2) 2.9
Noninverting input current noise f > 1 MHz 25°C 18 nV/√Hz B
25°C(1) 19
0°C to 70°C(2) 21
–40°C to +85°C(2) 22
Inverting input current noise f > 1 MHz 25°C 22 pA/√Hz B
25°C(1) 24
0°C to 70°C(2) 26
–40°C to +85°C(2) 27
DC PERFORMANCE(4)
Open-loop transimpedance gain (ZOL) VO = VS/2, RL = 100 Ω to VS/2 25°C 70 kΩ A
25°C(1) 40
0°C to 70°C(2) 38
–40°C to +85°C(2) 38
Input offset voltage VCM = VS/2 25°C ±0.3 mV A
25°C(1) ±3(6)
0°C to 70°C(2) ±3.5
–40°C to +85°C(2) ±4
Average offset voltage drift VCM = VS 0°C to 70°C(2) ±10 μV/°C B
–40°C to +85°C(2) ±15
Noninventing input bias current VCM = VS 25°C ±5 µA A
25°C(1) ±40(6)
0°C to 70°C(2) ±45
–40°C to +85°C(2) ±50
Average noninventing input bias current drift VCM = VS 0°C to 70°C(2) ±110 nA/°C B
–40°C to +85°C(2) ±170
Inverting input bias current VCM = VS 25°C ±5
25°C(1) ±60(6)
0°C to 70°C(2) ±66
–40°C to +85°C(2) ±70
Average inverting input bias current drift VCM = VS 0°C to 70°C(2) ±120 nA/°C B
–40°C to +85°C(2) ±160
INPUT
Least positive input voltage(5) 25°C 1.7 V A
25°C(1) 1.8(6)
0°C to 70°C(2) 1.9
–40°C to +85°C(2) 1.9
Most positive input voltage(5) 25°C 3.3 V A
25°C(1) 3.2(6)
0°C to 70°C(2) 3.1
–40°C to +85°C(2) 3.1
Common-mode rejection ratio (CMRR) VCM = VS/2 25°C 54 dB A
25°C(1) 51(6)
0°C to 70°C(2) 50
–40°C to +85°C(2) 50
Noinverting input impedance 25°C 280 || 1.2 kΩ || pF C
Inverting input resistance (Rl) Open-loop 25°C 32 Ω C
OUTPUT
Most positive output voltage No load 25°C 4.2 V A
25°C(1) 4.0(6)
0°C to 70°C(2) 3.9
–40°C to +85°C(2) 3.8
RL = 100 Ω to VS/2 25°C 4
25°C(1) 3.9(6)
0°C to 70°C(2) 3.8
–40°C to +85°C(2) 3.7
Least positive output voltage No load 25°C 0.8 V A
25°C(1) 1(6)
0°C to 70°C(2) 1.1
–40°C to +85°C(2) 1.2
RL = 100 Ω to VS/2 25°C 1
25°C(1) 1.1(6)
0°C to 70°C(2) 1.2
–40°C to +85°C(2) 1.3
Current output, sourcing VO = VS/2 25°C 90 mA A
25°C(1) 70(6)
0°C to 70°C(2) 67
–40°C to +85°C(2) 66
Current output, sinking VO = VS/2 25°C –90 mA A
25°C(1) –70(6)
0°C to 70°C(2) –67
–40°C to +85°C(2) –66
Closed-loop output impedance G = +2, f = 100 kHz 0.05 Ω C
DISABLE (Disabled LOW)
Power down supply current (+VS) VDIS = 0 25°C –95 µA C
25°C(1) –160
0°C to 70°C(2) –175
–40°C to +85°C(2) –180
Disable time 25°C 1 µs C
Enable time 25°C 25 ns C
Off isolation G = +8, 10 MHz 25°C 70 dB C
Output capacitance in disable 25°C 4 pF C
Tun on glitch G = +2, RL = 150 Ω, VIN = VS /2 25°C ±100 mV C
Turn off glitch G = +2, RL = 150 Ω, VIN = VS /2 25°C ±20 mV C
Enable voltage 25°C 3.3 V A
25°C(1) 3.5(6)
0°C to 70°C(2) 3.6
–40°C to +85°C(2) 3.7
Disable voltage 25°C 1.8 V A
25°C(1) 1.7(6)
0°C to 70°C(2) 1.6
–40°C to +85°C(2) 1.5
Control pin input bias current (DIS) VDIS = 0 25°C 75 µA C
25°C(1) 130
0°C to 70°C(2) 143
–40°C to +85°C(2) 149
POWER SUPPLY
Specified single-supply operating voltage 25°C 5 V C
Max single-supply operating voltage 25°C(1) 12(6) V A
0°C to 70°C(2) 12
–40°C to +85°C(2) 12
Max quiescent current VS = +5 V 25°C 11.4 mA A
25°C(1) 12(6)
0°C to 70°C(2) 12.5
–40°C to +85°C(2) 12.9
Min quiescent current VS = +5 V 25°C 11.4 mA A
25°C(1) 10.9(6)
0°C to 70°C(2) 9.4
–40°C to +85°C(2) 9.1
Power-supply rejection ratio (–PSRR) Input referred 25°C 56 dB A
TEMPERATURE RANGE
Specification: ID, IDBV 25°C –40 to +85 °C °C
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +15°C at high temperature limit for over temperature specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3 dB below minimum specified CMRR at ± CMIR limits.
(6) Limits are tested at +25°C.

6.6 Typical Characteristics

G = +8, RF = 402 Ω, RL = 100 Ω, unless otherwise noted.
OPA695 sbos293_typchar_1.gif
Figure 1. Noninverting Small-Signal Frequency Response
OPA695 sbos293_typchar_3.gif
Figure 3. Noninverting Large-Signal Frequency Response
OPA695 sbos293_typchar_5.gif
Figure 5. Noninverting Large and Small-Signal Frequency Response
OPA695 sbos293_typchar_7.gif
Figure 7. 10-MHz Harmonic Distortion vs Load Resistance
OPA695 sbos293_typchar_9.gif
Figure 9. Harmonic Distortion vs Frequency
OPA695 sbos293_typchar_11.gif
Figure 11. 10-MHz Harmonic Distortion vs Noninverting Gain
OPA695 sbos293_typchar_13.gif
Figure 13. Input Voltage and Current Noise Density
OPA695 sbos293_typchar_15.gif
Figure 15. Input Return Loss vs Frequency (S11)
OPA695 sbos293_typchar_17.gif
Figure 17. RS vs Capacitive Load
OPA695 sbos293_typchar_19.gif
Figure 19. CMRR and PSRR vs Frequency
OPA695 sbos293_typchar_21.gif
Figure 21. Output Voltage and Current Limitations
OPA695 sbos293_typchar_23.gif
Figure 23. Noninverting Overdrive Recovery
OPA695 sbos293_typchar_25.gif
Figure 25. Settling Time
OPA695 sbos293_typchar_27.gif
Figure 27. Typical DC Drift Over Temperature
OPA695 sbos293_typchar_29.gif
Figure 29. Composite Video dG/dφ
OPA695 sbos293_typchar_32.gif
See Figure 47
Figure 31. Differential Small-Signal Frequency Response
OPA695 sbos293_typchar_34.gif
Figure 33. Distortion vs Frequency
OPA695 sbos293_typchar_36.gif
Figure 35. 2-Tone, 3rd-Order Intermodulation Intercept
OPA695 sbos293_typchar_38.gif
Figure 37. Inverting Small-Signal Frequency Response
OPA695 sbos293_typchar_40.gif
Figure 39. Inverting Pulse Response
OPA695 sbos293_typchar_42.gif
Figure 41. Small-Signal Frequency Response vs Capacitive Load
OPA695 sbos293_typchar_44.gif
Figure 43. 10-MHz Harmonic Distortion vs Output Voltage
OPA695 sbos293_typchar_46.gif
Figure 45. Two-Tone, 3rd-Order Intermodulation Intercept
OPA695 sbos293_typchar_2.gif
Figure 2. Inverting Small-Signal Frequency Response
OPA695 sbos293_typchar_4.gif
Figure 4. Inverting Large-Signal Frequency Response
OPA695 sbos293_typchar_6.gif
Figure 6. Inverting Large and Small-Signal Frequency Response
OPA695 sbos293_typchar_8.gif
Figure 8. 10-MHz Harmonic Distortion vs Supply Voltage
OPA695 sbos293_typchar_10.gif
Figure 10. 10-MHz Harmonic Distortion vs Output Voltage
OPA695 sbos293_typchar_12.gif
Figure 12. 10-MHz Harmonic Distortion vs Inverting Gain
OPA695 sbos293_typchar_14.gif
Figure 14. Two-Tone 3rd-Order Intermodulation Intercept ±5 V
OPA695 sbos293_typchar_16.gif
Figure 16. Output Return Loss vs Frequency (S22)
OPA695 sbos293_typchar_18.gif
Figure 18. Small-Signal Frequency Response vs Capacitive Load
OPA695 sbos293_typchar_20.gif
Figure 20. Open-Loop Transimpedance Gain and Phase
OPA695 sbos293_typchar_22.gif
Figure 22. Supply and Output Current vs Temperature
OPA695 sbos293_typchar_24.gif
Figure 24. Inverting Overdrive Recovery
OPA695 sbos293_typchar_26.gif
Figure 26. Disabled Feedthrough vs Frequency
OPA695 sbos293_typchar_28.gif
Figure 28. Common-Mode Input and Output Swing vs Supply Voltage
OPA695 sbos293_typchar_30.gif
Figure 30. Large-Signal Disable/Enable Response
OPA695 sbos293_typchar_33.gif
Figure 32. Large-Signal Bandwidth
OPA695 sbos293_typchar_35.gif
Figure 34. Distortion vs VOUT
OPA695 sbos293_typchar_37.gif
Figure 36. Noninverting Small-Signal Frequency Response
OPA695 sbos293_typchar_39.gif
Figure 38. Noninverting Pulse Response
OPA695 sbos293_typchar_41.gif
Figure 40. RS vs Capacitive Load
OPA695 sbos293_typchar_43.gif
Figure 42. Harmonic Distortion vs Frequency
OPA695 sbos293_typchar_45.gif
Figure 44. 10-MHz Harmonic Distortion vs Load Resistance
OPA695 sbos293_typchar_47.gif
Figure 46. Small-Signal BW vs Single-Supply Voltage