ZHCSSC0F January   2001  – October 2023 OPA561

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Feature Description
      1. 6.2.1 Adjustable Current Limit
        1. 6.2.1.1 Current Limit Accuracy
        2. 6.2.1.2 Setting the Current Limit
      2. 6.2.2 Enable-Status (E/S) Pin
        1. 6.2.2.1 Output Disable
        2. 6.2.2.2 Maintaining Microcontroller Compatibility
      3. 6.2.3 Overcurrent Flag
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Output Stage Compensation
      2. 7.1.2 Output Protection
      3. 7.1.3 Thermal Protection
      4. 7.1.4 Power Dissipation
      5. 7.1.5 Heat-Sink Area
      6. 7.1.6 Amplifier Mounting
        1. 7.1.6.1 What is the PowerPAD™ Integrated Circuit Package?
        2. 7.1.6.2 PowerPAD™ Integrated Circuit Package Assembly Process
    2. 7.2 Typical Application
      1. 7.2.1 Laser Diode Driver
      2. 7.2.2 Programmable Power Supply
      3. 7.2.3 Power-Line Communication Modem
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 第三方产品免责声明
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.2.2.1 Output Disable

The shutdown pin is referenced to the negative supply (V−). Therefore, shutdown operation is slightly different in single-supply and dual-supply applications. In single-supply operation, V− typically equals common ground. Therefore, the shutdown logic signal and the OPA561’s shutdown pin are referenced to the same potential. In this configuration, the logic pin and the OPA561 enable can simply be tied together. Shutdown occurs for voltage levels of < 0.8 V. The OPA561 is enabled at logic levels > 2 V. In dual-supply operation, the logic pin is still referenced to a logic ground. However, the shutdown pin of the OPA561 is still referenced to V−. To shutdown the OPA561, the voltage level of the logic signal needs to be level shifted using an optocoupler, as shown in Figure 6-2.

GUID-20230614-SS0I-Q5DH-LJ4C-2V2SCH5W4FJT-low.svg Figure 6-2 Shutdown Configuration for Dual Supplies

To disable the output, the E/S pin is pulled LOW, to no greater than 0.8 V above V−. This function can be used to conserve power during idle periods. The typical time required to shut down the output is 50 ns. To return the output to an enabled state, the E/S pin can be pulled to at least 2.0 V above V−. Typically, the output is enabled within 3 μs. Note that pulling the E/S pin HIGH (output enabled) does not disable the internal thermal shutdown.