ZHCSER2D 数据表 | 德州仪器 TI.com.cn

ZHCSER2D May 2013 – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RGC|64
- MPQF125F

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND102O

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9.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-1). The vector contains the 16-bit address of the interrupt-handler instruction sequence.

Table 9-1 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power up External reset Watchdog time-out, password violation Flash memory password violation PMM password violation	WDTIFG, KEYV (SYSRSTIV)⁽¹⁾ ⁽³⁾	Reset	0FFFEh	63, highest
System NMI PMM Vacant memory access JTAG mailbox	SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)⁽¹⁾	(Non)maskable	0FFFCh	62
User NMI NMI Oscillator fault Flash memory access violation	NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)⁽¹⁾ ⁽³⁾	(Non)maskable	0FFFAh	61
COMP_B	Comparator B interrupt flags (CBIV)⁽¹⁾ ⁽²⁾	Maskable	0FFF8h	60
USCI_A0 receive or transmit	UCA0RXIFG, UCA0TXIFG (UCA0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFF6h	59
USCI_B0 receive or transmit	UCB0RXIFG, UCB0TXIFG (UCB0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFF4h	58
Watchdog timer interval timer mode	WDTIFG	Maskable	0FFF2h	57
USCI_A1 receive or transmit	UCA1RXIFG, UCA1TXIFG (UCA1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFF0h	56
USCI_B1 receive or transmit	UCB1RXIFG, UCB1TXIFG (UCB1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFEEh	55
ADC10_A	ADC10IFG0⁽¹⁾ ⁽²⁾ ⁽⁵⁾	Maskable	0FFECh	54
USCI_A2 receive or transmit	UCA2RXIFG, UCA2TXIFG (UCA2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFEAh	53
USCI_B2 receive or transmit	UCB2RXIFG, UCB2TXIFG (UCB2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFE8h	52
TA0	TA0CCR0 CCIFG0⁽²⁾	Maskable	0FFE6h	51
TA0	TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFE4h	50
Reserved	Reserved⁽⁴⁾	Maskable	0FFE2h	49
DMA	DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)⁽¹⁾ ⁽²⁾	Maskable	0FFE0h	48
USCI_A3 receive or transmit	UCA3RXIFG, UCA3TXIFG (UCA3IV)⁽¹⁾ ⁽²⁾	Maskable	0FFDEh	47
USCI_B3 receive or transmit	UCB3RXIFG, UCB3TXIFG (UCB3IV)⁽¹⁾ ⁽²⁾	Maskable	0FFDCh	46
TB0	TB0CCR0 CCIFG0 ⁽²⁾	Maskable	0FFDAh	45
TB0	TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TB0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD8h	44
TA1	TA1CCR0 CCIFG0⁽²⁾	Maskable	0FFD6h	43
TA1	TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD4h	42
I/O port P1	P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD2h	41
TA2	TA2CCR0 CCIFG0⁽²⁾	Maskable	0FFD0h	40
TA2	TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFCEh	39
I/O port P2	P2IFG.0 to P2IFG.7 (P2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFCCh	38
RTC_A	RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)⁽¹⁾ ⁽²⁾	Maskable	0FFCAh	37
I/O Port P6	P6IFG.0 to P6IFG.7 (P6IV)⁽¹⁾ ⁽²⁾	Maskable	0FFC8h	36
Reserved	Reserved⁽⁴⁾		0FFC6h	35
			⋮	⋮
			0FF80h	0, lowest

(1) Multiple source flags

(2) Interrupt flags are in the module.

(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.

(5) Only on devices with ADC, otherwise reserved