ZHCSAJ5 数据表 | 德州仪器 TI.com.cn

ZHCSAJ5H November 2012 – September 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND031W

订购信息

5.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage during program execution and flash programming (AVCC = DVCC)⁽¹⁾⁽³⁾⁽²⁾	PMMCOREVx = 0	1.8		3.6	V
		PMMCOREVx = 0, 1	2.0		3.6
		PMMCOREVx = 0, 1, 2	2.2		3.6
		PMMCOREVx = 0, 1, 2, 3	2.4		3.6
V_IO	Supply voltage applied to DVIO referenced to V_SS⁽³⁾		1.62		1.98	V
V_SS	Supply voltage (AVSS = DVSS)			0		V
T_A	Operating free-air temperature		–40		85	°C
T_J	Operating junction temperature		–40		85	°C
C_VCORE	Recommended capacitor at VCORE⁽⁴⁾			470		nF
C_DVCC/ C_VCORE	Capacitor ratio of DVCC to VCORE		10
f_SYSTEM	Processor frequency (maximum MCLK frequency)⁽⁵⁾ (see Figure 5-3)	PMMCOREVx = 0 (default condition), 1.8 V ≤ V_CC ≤ 3.6 V	0		8	MHz
		PMMCOREVx = 1, 2.0 V ≤ V_CC ≤ 3.6 V	0		12
		PMMCOREVx = 2, 2.2 V ≤ V_CC ≤ 3.6 V	0		20
		PMMCOREVx = 3, 2.4 V ≤ V_CC ≤ 3.6 V	0		25

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for the exact values and further details.

(3) During V_CC and V_IO power up, it is required that V_IO ≥ V_CC during the ramp up phase of V_IO. During V_CC and V_IO power down, it is required that V_IO ≥ V_CC during the ramp down phase of V_IO (see Figure 5-1).

(4) A capacitor tolerance of ±20% or better is required.

(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 slas718-power_sequence_update.gif

NOTE:

The device supports continuous operation with V_CC= V_SS while V_IO is fully within its specification. During this time, the general-purpose I/Os that reside on the V_IO supply domain are configured as inputs and pulled down to V_SS through their internal pulldown resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to V_SS through its internal pulldown resistor. When V_CCreaches above the BOR threshold, the general-purpose I/Os become high-impedance inputs (no resistor enabled), RST/NMI becomes an input pulled up to V_IO through its internal pullup resistor, and BSLEN remains pulled down to V_SS through its internal pulldown resistor.

NOTE:

Under certain condtions during the rising transition of V_CC, the general-purpose I/Os residing on the V_IO supply domain may actively transition high momentarily before settling to high-impedance inputs. These voltage transitions are temporary (typically resolving to high-impedance inputs when V_CC exceeds approximately 0.9 V) and are bounded by the V_IO supply.

Figure 5-1 V_CC and V_IO Power Sequencing

MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 slas718-reset_timing.gif

NOTE:

The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on DVCC voltage supply. If RSTDVCC or RST is held at a logic low or if DVCC is below the SVSH_+ minimum threshold, the device remains in its reset condition; that is, these conditions form a logical OR with respect to device reset.

Figure 5-2 Reset Timing

MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217 MSP430F5214 MSP430F5212 slas590-op_cond.gif

Figure 5-3 Maximum System Frequency