7.3.1.1 Multi-Phase Operation and Phase-Shedding

Under heavy load conditions, the switching phase of the bucks are interleaved. As a result, the 6-phase converter has higher effective switching frequency than the switching frequency of any one phase.

The parallel operation decreases the efficiency at low load conditions. In order to overcome this operational inefficiency, the LP8754 automatically changes the number of active phases to maximize the efficiency. This is called phase-shedding and the concept is illustrated in Figure 9.

Figure 9. Multi-phase Buck Converter Efficiency vs Number of Phases; All Converters in PWM Mode

(1) Graph is not to scale and is for illustrative purposes only.

7.3.1.2 Transitions Between Low-Power PFM, PFM, and PWM Modes

Normal PWM-mode operation with phase-shedding can optimize efficiency at mid-to-full load, but this is usually at the expense of light-load efficiency. The LP8754 converter operates in PWM mode at a load current of 100 to 375 mA or higher; this mode transition trip-point is set by register. Lighter load current causes the device to automatically switch into PFM mode for reduced current consumption. By combining PFM and PWM modes in the same regulator and providing automatic switching, high efficiency can be achieved over a wide output load current range.

Efficiency is further enhanced when the converter enters Low-Power PFM mode. The LP8754 includes Low-Power mode function for low-current consumption. In this mode most of the internal blocks are disabled between the inductor current ramp up and ramp down phases to reduce the operating current. However, as a result, the transient performance of the converter is compromised. The Low-Power mode can be enabled by control register setting. Also, the application processor or the PMIC may provide an HW signal (NSLP) to the LP8754 input to indicate when the processor has entered a low-power state. When the signal is asserted, the LP8754 Low-Power PFM function will be enabled, and the LP8754 will run with a reduced input current. The right timing of the NSLP signal from the system is important for best load-transient performance. The NSLP signal should be asserted only when load current is stable and below 30 mA. Before the load current increases above 30 mA, the NSLP signal should be de-asserted 100 µs (minimum) prior to a load step to prepare the converter for the higher load current.

7.3.1.3 Buck Converter Load Current

The buck load current can be monitored via I²C registers. Current of different buck converter cores or the total load current of the master can be selected from register 0x21 (see SEL_I_LOAD). A write to this selection register starts a current measurement sequence. The measurement sequence is a minimum of 50 µs long. When a measurement sequence starts, the FLAGS_1.I_LOAD_READY bit in register 0x0E is set to '0'. After the measurement sequence is finished, the FLAGS_1.I_LOAD_READY bit is set to '1'. (Note that by default this bit is '0'.) The measurement result can be read from registers 0x22 (LOAD_CURR.BUCK_LOAD_CURR[7:0]) and 0x21 (SEL_I_LOAD.BUCK_LOAD_CURR[10:8]). The measurement result [10:0] LSB is 10 mA, and the maximum value of the measurement is 20 A. The LP8754 can be configured to give out an interrupt after the load current measurement sequence is finished. Load current measurement interrupt can be masked with INT_MASKS_2.MASK_I_LOAD_READY bit.

7.3.1.4 Spread Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The LP8754's register-selectable spread spectrum mode minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies randomly around the center frequency, reducing the EMI emissions radiated by the converter, associated passive components, and PCB traces. See Figure 10.

Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the LP8754 spreads that energy over a large bandwidth.

Figure 10. Spread Spectrum Modulation

Table 1. Power-Up Sequence

Table 2. Hardware Reset, Power-On Reset (POR) and Software Reset: Registers After Reset

Table 3. Summary of Exceptions and Interrupt Signals

7.3.4.1 Warnings for Diagnosis (No Power Down)

Masking time for start-up is constant 400 µs (typ.). Masking time for voltage transitions depends on the selected ramp rates.

Figure 16. Power Good Masking Principle

7.3.4.2 Faults (Fault State and Fast Power Down)

7.3.4.2.3 Thermal Shutdown (THSD)

The LP8754 has a thermal overload protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the device enters shutdown via fault-state. INT will be cleared upon write of the FLAGS_1.THSD flag even when thermal shutdown is active. This allows automatic recovery when temperature decreases below thermal shutdown level. See Figure 17 for LP8754 thermal diagnosis and protection features.

Note that INT is asserted whenever any of the thermal thresholds is crossed, if unmasked. Note also the 10°C Hysteresis on the T_J Thresholds.

Figure 17. Thermal Warnings and Thermal Shutdown Flow

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when clock signal is LOW.

Figure 19. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

The LP8754 is controlled via an I²C-compatible interface. START and STOP conditions classify the beginning and end of the I²C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I²C master always generates the START and STOP conditions.

Figure 20. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I²C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 1 shows the SDA and SCL signal timing for the I²C-Compatible Bus. See the I2C Serial Bus Timing Parameters for timing values.

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8754 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8754 generates an acknowledge after each byte has been received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

Figure 21. Write Cycle (w = write; SDA = '0'), id = device address = 60Hex for LP8754.

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 22. Read Cycle ( r = read; SDA = '1'), id = device address = 60Hex for LP8754.

7.5.1.4 I²C-Compatible Chip Address

The device address for the LP8754 is 0x60 (ADDR pin tied to the GND). After the START condition, the I²C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.

Here device address is 1100000Bin = 60 Hex.

Figure 23. Device Address

7.5.1.5 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the LP8754, the internal address index counter will be incremented by one, and the next register will be written. Table 4 shows writing sequence to two consecutive registers. Note: the auto-increment feature does not work for read.

Table 5. Register Descriptions