ZHCSDB8A February   2014  – August 2014 LP8754

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  General Electrical Characteristics
    6. 6.6  6-Phase Buck Electrical Characteristics
    7. 6.7  6-Phase Buck System Characteristics
    8. 6.8  Protection Features Characteristics
    9. 6.9  I2C Serial Bus Timing Parameters
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
    2. 7.2 Functional Block Diagram
    3. 7.3 Features Descriptions
      1. 7.3.1 Multi-Phase DC-DC Converters
        1. 7.3.1.1 Multi-Phase Operation and Phase-Shedding
        2. 7.3.1.2 Transitions Between Low-Power PFM, PFM, and PWM Modes
        3. 7.3.1.3 Buck Converter Load Current
        4. 7.3.1.4 Spread Spectrum Mode
      2. 7.3.2 Power-Up and Output Voltage Sequencing
      3. 7.3.3 Device Reset Scenarios
      4. 7.3.4 Diagnosis and Protection Features
        1. 7.3.4.1 Warnings for Diagnosis (No Power Down)
          1. 7.3.4.1.1 Short-Circuit Protection (SCP)
          2. 7.3.4.1.2 Power Good Monitoring
          3. 7.3.4.1.3 Thermal Warnings
        2. 7.3.4.2 Faults (Fault State and Fast Power Down)
          1. 7.3.4.2.1 Undervoltage Lockout (UVLO)
          2. 7.3.4.2.2 Overvoltage Protection (OVP)
          3. 7.3.4.2.3 Thermal Shutdown (THSD)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1  Register Descriptions
      2. 7.6.2  VSET_B0
      3. 7.6.3  FPWM
      4. 7.6.4  BUCK0_CTRL
      5. 7.6.5  BUCK1_CTRL
      6. 7.6.6  BUCK2_CTRL
      7. 7.6.7  BUCK3_CTRL
      8. 7.6.8  BUCK4_CTRL
      9. 7.6.9  BUCK5_CTRL
      10. 7.6.10 FLAGS_0
      11. 7.6.11 FLAGS_1
      12. 7.6.12 INT_MASK_0
      13. 7.6.13 GENERAL
      14. 7.6.14 RESET
      15. 7.6.15 DELAY_BUCK0
      16. 7.6.16 CHIP_ID
      17. 7.6.17 PFM_LEV_B0
      18. 7.6.18 PHASE_LEV_B0
      19. 7.6.19 SEL_I_LOAD
      20. 7.6.20 LOAD_CURR
      21. 7.6.21 INT_MASK_2
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 LDO Capacitor Selection
        5. 8.2.2.5 VIOSYS Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DSBGA (YFQ)
49 Pins
Top View
LP8754 po49CSP_Top_SNAS580.gif

Pin Functions

PIN TYPE DESCRIPTION
NUMBER NAME
A1, B1 VINB2 P Input for Buck 2. The separate power pins VINBXX are not connected together internally - VINBXX pins must be connected together in the application and be locally bypassed.
A2, B2 SWB2 A Buck 2 switch node
A3, B3, C3 GNDB1/B2 G Power Ground for Buck 1 and Buck 2
A4, B4 SWB1 A Buck 1 switch node
A5, B5, C5 VINB0/B1 P Input for Buck 0 and Buck 1. The separate power pins VINBXX are not connected together internally - VINBXX pins must be connected together in the application and be locally bypassed.
A6, B6 SWB0 A Buck 0 switch node
A7, B7 GNDB0 G Power Ground for Buck 0
C1 SDASYS D/I/O Serial interface data input and output for system access. Connect a pullup resistor.
C2 SCLSYS D/I Serial interface clock input for system access. Connect a pullup resistor.
C4 ADDR D/I Serial bus address selection. Connect to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr = 62h) or SCLSYS (addr = 63h).
C6 NSLP D/I Full Power to Low Power state transition control signal (By default active LOW for Low-Power PFM mode)
C7 VLDO A Internal supply voltage capacitor pin. A ceramic low ESR 1-µF capacitor should be connected from this pin to GNDA. The LDO voltage is generated internally, do NOT supply or load this pin externally.
D1 FBB5 A Not used for six-phase converter. Connect to GND.
D2 FBB3−/B4 A Not used for six-phase converter. Connect to GND.
D3 FBB3+/B3 A Not used for six-phase converter. Connect to GND.
D4 FBB2 A Not used for six-phase converter. Connect to GND.
D5 FBB0−/B1 A Remote sensing (negative). Connect to the respective sense pin of the processor or to the negative power supply trace of the processor as close as possible to the processor.
D6 FBB0+/B0 A Remote sensing (positive). Connect to the respective sense pin of the processor or to the positive power supply trace of the processor as close as possible to the processor.
D7 GNDA G Ground
E1 SDASR D/I/O Serial Interface data input and output for Dynamic Voltage Scaling (DVS). Connect a pullup resistor / connect to GND if not used.
E2 SCLSR D/I Serial Interface clock input for DVS. Connect a pullup resistor / connect to GND if not used.
E3, F3, G3 GNDB4/B5 G Power Ground for Buck 4 and Buck 5
E4 NRST A Voltage reference input for DVS interface. Setting NRST input HIGH triggers start-up sequence.
E5, F5, G5 VINB3/B4 P Input for Buck 3 and Buck 4.The separate power pins VINBXX are not connected together internally - VINBXX pins must be connected together in the application and be locally bypassed.
E6 INT D/O Open-drain interrupt output. Active LOW. Connect a pullup resistor to I/O supply.
E7 VIOSYS A This pin shall be tied to the system I/O-voltage. Bias supply voltage for the device. Enables the I/O interface: All registers are accessible via serial bus interface when this pin is pulled high. An internal power-on reset (POR) occurs when VIOSYS is toggled low/high. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line.
F1 VDDA5V P Input for Analog blocks
F2, G2 SWB5 A Buck 5 switch node
F4, G4 SWB4 A Buck 4 switch node
F6, G6 SWB3 A Buck 3 switch node
F7, G7 GNDB3 G Power Ground for Buck 3
G1 VINB5 P Input for Buck 5. The separate power pins VINBXX are not connected together internally - VINBXX pins must be connected together in the application and be locally bypassed.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin