SNVS458D June   2007  – October 2016 LP55281

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 I2C Timing Requirements
    8. 6.8 Boost Converter Typical Characteristics
    9. 6.9 RGB Driver Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Magnetic Boost DC-DC Converter
        1. 7.3.1.1 Boost Standby Mode
        2. 7.3.1.2 Boost Output Voltage Control
        3. 7.3.1.3 Boost Frequency Control
      2. 7.3.2 Functionality of RGB LED Outputs (R1-4, G1-4, B1-4)
        1. 7.3.2.1 PWM Control Timing
      3. 7.3.3 Audio Synchronization
        1. 7.3.3.1 Control of Audio Synchronization
        2. 7.3.3.2 ALED Driver
          1. 7.3.3.2.1 Adjustment of ALED Driver
      4. 7.3.4 LED Test Interface
        1. 7.3.4.1 LED Test Procedure
        2. 7.3.4.2 LED Test Time Estimation
      5. 7.3.5 7-V Shielding
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes Of Operation
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 I2C Compatible Serial Bus Interface
        1. 7.5.2.1 Interface Bus Overview
        2. 7.5.2.2 Data Transactions
        3. 7.5.2.3 Acknowledge Cycle
        4. 7.5.2.4 Acknowledge After Every Byte Rule
        5. 7.5.2.5 Addressing Transfer Formats
        6. 7.5.2.6 Control Register Write Cycle
        7. 7.5.2.7 Control Register Read Cycle
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Recommended External Components
          1. 8.2.2.1.1 Output Capacitor, COUT
          2. 8.2.2.1.2 List Of Recommended External Components
          3. 8.2.2.1.3 Input Capacitor, CIN
          4. 8.2.2.1.4 Output Diode, D1
          5. 8.2.2.1.5 Inductor, L
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Inductor Placement
      4. 10.1.4 Boost Input Capacitor Placement
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

The inductive boost converter of the LP55281 regulates a switched voltage at the SW pin, and a step current (up to ICL) through the Schottky diode and output capacitor each switching cycle. The switching voltage can create interference into nearby nodes due to electric field coupling (I = CdV/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW pin and the OUT pin due to parasitic inductance in the step current conducting path (V = Ldi/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise.

The following list details the main (layout sensitive) areas of the LP55281 device's inductive boost converter in order of decreasing importance:

  • Output Capacitor
    • Schottky cathode to COUT+
    • COUT– to GND
  • Schottky Diode
    • SW pin to Schottky anode
    • Schottky Cathode to COUT+
  • Inductor
    • SW Node PCB capacitance to other traces
  • Input Capacitor
    • CIN+ to IN pin

10.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path it detects a high-current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any parasitic inductance (LP_) along this series path from the cathode of the diode through COUT and back into the GND pin of the LP55281 device GND pin contributes to voltage spikes (VSPIKE = LP_ × di/dt) at SW and FB. These spikes can potentially over-voltage the SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close as possible to the cathode of the Schottky diode, and COUT− must be connected as close the the GND pin of the device as possible. The best placement for COUT is on the same layer as the LP55281 in order to avoid any vias that can add excessive series inductance.

10.1.2 Schottky Diode Placement

In the boost circuit of the LP55281 device the Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any parasitic inductance (LP) in series with the diode causes a voltage spike (VSPIKE = LP × di/dt) at SW and OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor and into GND. Connecting the anode of the diode as close as possible to the SW pin and the cathode of the diode as close as possible to COUT and reduces the parasitic inductance and minimize these voltage spikes.

10.1.3 Inductor Placement

The node where the inductor connects to the LP55281 device's SW pin has 2 concerns. First, the switched voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range. To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not directly adjacent or beneath. This is especially true for sensitive analog signals (ASE1, ASE2, FB, IRT, IRGB, VREF). A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces. Lastly, limit the trace resistance of the VIN to inductor connection and from the inductor to SW connection, by use of short, wide traces.

10.1.4 Boost Input Capacitor Placement

Close placement of the input capacitor to the IN pin and to the GND pin is critical because any series inductance between IN and CIN+ or CIN− and GND can create voltage spikes that could appear on the VIN supply line and in the GND plane. Close placement of the input bypass capacitor at the input side of the inductor is also critical.

10.2 Layout Example

LP55281 LayoutExample.gif Figure 32. LP55281 Layout